Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469380 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46013 |
| auto[1] |
5493749 |
1 |
|
|
T1 |
35955 |
|
T11 |
81 |
|
T16 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10652020 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
68604 |
| auto[1] |
2311109 |
1 |
|
|
T1 |
13364 |
|
T11 |
88 |
|
T16 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7473413 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44292 |
| auto[1] |
5489716 |
1 |
|
|
T1 |
37676 |
|
T11 |
130 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1589713 |
1 |
|
|
T1 |
12610 |
|
T11 |
28 |
|
T12 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1156938 |
1 |
|
|
T1 |
6880 |
|
T11 |
59 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1588894 |
1 |
|
|
T1 |
11702 |
|
T11 |
14 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1154171 |
1 |
|
|
T1 |
6484 |
|
T11 |
29 |
|
T16 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |