Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476598 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45639 |
| auto[1] |
5486531 |
1 |
|
|
T1 |
36329 |
|
T11 |
149 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10647089 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69183 |
| auto[1] |
2316040 |
1 |
|
|
T1 |
12785 |
|
T11 |
78 |
|
T16 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7455513 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45335 |
| auto[1] |
5507616 |
1 |
|
|
T1 |
36633 |
|
T11 |
154 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1594144 |
1 |
|
|
T1 |
11787 |
|
T11 |
28 |
|
T17 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1157166 |
1 |
|
|
T1 |
6403 |
|
T11 |
39 |
|
T16 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1597432 |
1 |
|
|
T1 |
12061 |
|
T11 |
48 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1158874 |
1 |
|
|
T1 |
6382 |
|
T11 |
39 |
|
T16 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |