Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7491741 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44899 |
| auto[1] |
5471388 |
1 |
|
|
T1 |
37069 |
|
T11 |
141 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10656105 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69628 |
| auto[1] |
2307024 |
1 |
|
|
T1 |
12340 |
|
T11 |
79 |
|
T16 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7475566 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44942 |
| auto[1] |
5487563 |
1 |
|
|
T1 |
37026 |
|
T11 |
117 |
|
T16 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1595812 |
1 |
|
|
T1 |
12374 |
|
T11 |
18 |
|
T16 |
19 |
| auto[1] |
auto[0] |
auto[1] |
1156083 |
1 |
|
|
T1 |
6205 |
|
T11 |
47 |
|
T16 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1584727 |
1 |
|
|
T1 |
12312 |
|
T11 |
20 |
|
T16 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1150941 |
1 |
|
|
T1 |
6135 |
|
T11 |
32 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |