Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7490904 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46265 |
| auto[1] |
5472225 |
1 |
|
|
T1 |
35703 |
|
T11 |
92 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10649905 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
68591 |
| auto[1] |
2313224 |
1 |
|
|
T1 |
13377 |
|
T11 |
51 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476426 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45614 |
| auto[1] |
5486703 |
1 |
|
|
T1 |
36354 |
|
T11 |
130 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1582500 |
1 |
|
|
T1 |
11702 |
|
T11 |
50 |
|
T16 |
17 |
| auto[1] |
auto[0] |
auto[1] |
1157594 |
1 |
|
|
T1 |
6724 |
|
T11 |
31 |
|
T16 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1590979 |
1 |
|
|
T1 |
11275 |
|
T11 |
29 |
|
T16 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1155630 |
1 |
|
|
T1 |
6653 |
|
T11 |
20 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |