Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7458067 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45462 |
| auto[1] |
5505062 |
1 |
|
|
T1 |
36506 |
|
T11 |
123 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10657120 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69637 |
| auto[1] |
2306009 |
1 |
|
|
T1 |
12331 |
|
T11 |
65 |
|
T16 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7494548 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46997 |
| auto[1] |
5468581 |
1 |
|
|
T1 |
34971 |
|
T11 |
114 |
|
T16 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1576901 |
1 |
|
|
T1 |
11262 |
|
T11 |
27 |
|
T16 |
6 |
| auto[1] |
auto[0] |
auto[1] |
1151315 |
1 |
|
|
T1 |
6251 |
|
T11 |
38 |
|
T16 |
10 |
| auto[1] |
auto[1] |
auto[0] |
1585671 |
1 |
|
|
T1 |
11378 |
|
T11 |
22 |
|
T129 |
199 |
| auto[1] |
auto[1] |
auto[1] |
1154694 |
1 |
|
|
T1 |
6080 |
|
T11 |
27 |
|
T16 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |