Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7503188 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45674 |
| auto[1] |
5459941 |
1 |
|
|
T1 |
36294 |
|
T11 |
120 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10658676 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
68272 |
| auto[1] |
2304453 |
1 |
|
|
T1 |
13696 |
|
T11 |
57 |
|
T16 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7480225 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
43409 |
| auto[1] |
5482904 |
1 |
|
|
T1 |
38559 |
|
T11 |
136 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1600609 |
1 |
|
|
T1 |
13164 |
|
T11 |
40 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
1157166 |
1 |
|
|
T1 |
7056 |
|
T11 |
32 |
|
T16 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1577842 |
1 |
|
|
T1 |
11699 |
|
T11 |
39 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1147287 |
1 |
|
|
T1 |
6640 |
|
T11 |
25 |
|
T16 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |