Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442397 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46616 |
| auto[1] |
5520732 |
1 |
|
|
T1 |
35352 |
|
T11 |
163 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10650193 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69411 |
| auto[1] |
2312936 |
1 |
|
|
T1 |
12557 |
|
T11 |
72 |
|
T16 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459032 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46321 |
| auto[1] |
5504097 |
1 |
|
|
T1 |
35647 |
|
T11 |
137 |
|
T16 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1597387 |
1 |
|
|
T1 |
12547 |
|
T11 |
36 |
|
T16 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1156170 |
1 |
|
|
T1 |
7016 |
|
T11 |
30 |
|
T16 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1593774 |
1 |
|
|
T1 |
10543 |
|
T11 |
29 |
|
T16 |
13 |
| auto[1] |
auto[1] |
auto[1] |
1156766 |
1 |
|
|
T1 |
5541 |
|
T11 |
42 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |