Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476119 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45630 |
| auto[1] |
5487010 |
1 |
|
|
T1 |
36338 |
|
T11 |
91 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12264557 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
77984 |
| auto[1] |
698572 |
1 |
|
|
T1 |
3984 |
|
T11 |
5 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7496521 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45612 |
| auto[1] |
5466608 |
1 |
|
|
T1 |
36356 |
|
T11 |
101 |
|
T12 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2388993 |
1 |
|
|
T1 |
15866 |
|
T11 |
61 |
|
T12 |
8 |
| auto[1] |
auto[0] |
auto[1] |
349630 |
1 |
|
|
T1 |
1934 |
|
T11 |
4 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2379043 |
1 |
|
|
T1 |
16506 |
|
T11 |
35 |
|
T16 |
6 |
| auto[1] |
auto[1] |
auto[1] |
348942 |
1 |
|
|
T1 |
2050 |
|
T11 |
1 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |