Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4724160	1			T23	81		T24	868		T25	77
all_pins[1]	4724160	1			T23	81		T24	868		T25	77
all_pins[2]	4724160	1			T23	81		T24	868		T25	77
all_pins[3]	4724160	1			T23	81		T24	868		T25	77
all_pins[4]	4724160	1			T23	81		T24	868		T25	77
all_pins[5]	4724160	1			T23	81		T24	868		T25	77
all_pins[6]	4724160	1			T23	81		T24	868		T25	77
all_pins[7]	4724160	1			T23	81		T24	868		T25	77
all_pins[8]	4724160	1			T23	81		T24	868		T25	77
all_pins[9]	4724160	1			T23	81		T24	868		T25	77
all_pins[10]	4724160	1			T23	81		T24	868		T25	77
all_pins[11]	4724160	1			T23	81		T24	868		T25	77
all_pins[12]	4724160	1			T23	81		T24	868		T25	77
all_pins[13]	4724160	1			T23	81		T24	868		T25	77
all_pins[14]	4724160	1			T23	81		T24	868		T25	77
all_pins[15]	4724160	1			T23	81		T24	868		T25	77
all_pins[16]	4724160	1			T23	81		T24	868		T25	77
all_pins[17]	4724160	1			T23	81		T24	868		T25	77
all_pins[18]	4724160	1			T23	81		T24	868		T25	77
all_pins[19]	4724160	1			T23	81		T24	868		T25	77
all_pins[20]	4724160	1			T23	81		T24	868		T25	77
all_pins[21]	4724160	1			T23	81		T24	868		T25	77
all_pins[22]	4724160	1			T23	81		T24	868		T25	77
all_pins[23]	4724160	1			T23	81		T24	868		T25	77
all_pins[24]	4724160	1			T23	81		T24	868		T25	77
all_pins[25]	4724160	1			T23	81		T24	868		T25	77
all_pins[26]	4724160	1			T23	81		T24	868		T25	77
all_pins[27]	4724160	1			T23	81		T24	868		T25	77
all_pins[28]	4724160	1			T23	81		T24	868		T25	77
all_pins[29]	4724160	1			T23	81		T24	868		T25	77
all_pins[30]	4724160	1			T23	81		T24	868		T25	77
all_pins[31]	4724160	1			T23	81		T24	868		T25	77

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	93812246	1			T23	1398		T24	16986		T25	1256
values[0x1]	57360874	1			T23	1194		T24	10790		T25	1208
transitions[0x0=>0x1]	34344628	1			T23	619		T24	6443		T25	606
transitions[0x1=>0x0]	34344476	1			T23	618		T24	6442		T25	605

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2938202	1			T23	46		T24	468		T25	33
all_pins[0]	values[0x1]	1785958	1			T23	35		T24	400		T25	44
all_pins[0]	transitions[0x0=>0x1]	1102786	1			T23	19		T24	256		T25	25
all_pins[0]	transitions[0x1=>0x0]	1113905	1			T23	27		T24	197		T25	17
all_pins[1]	values[0x0]	2924284	1			T23	44		T24	511		T25	33
all_pins[1]	values[0x1]	1799876	1			T23	37		T24	357		T25	44
all_pins[1]	transitions[0x0=>0x1]	1080943	1			T23	23		T24	187		T25	19
all_pins[1]	transitions[0x1=>0x0]	1067025	1			T23	21		T24	230		T25	19
all_pins[2]	values[0x0]	2934775	1			T23	47		T24	520		T25	36
all_pins[2]	values[0x1]	1789385	1			T23	34		T24	348		T25	41
all_pins[2]	transitions[0x0=>0x1]	1068711	1			T23	18		T24	201		T25	20
all_pins[2]	transitions[0x1=>0x0]	1079202	1			T23	21		T24	210		T25	23
all_pins[3]	values[0x0]	2937233	1			T23	55		T24	587		T25	34
all_pins[3]	values[0x1]	1786927	1			T23	26		T24	281		T25	43
all_pins[3]	transitions[0x0=>0x1]	1069656	1			T23	14		T24	180		T25	21
all_pins[3]	transitions[0x1=>0x0]	1072114	1			T23	22		T24	247		T25	19
all_pins[4]	values[0x0]	2935955	1			T23	52		T24	501		T25	36
all_pins[4]	values[0x1]	1788205	1			T23	29		T24	367		T25	41
all_pins[4]	transitions[0x0=>0x1]	1072784	1			T23	18		T24	240		T25	17
all_pins[4]	transitions[0x1=>0x0]	1071506	1			T23	15		T24	154		T25	19
all_pins[5]	values[0x0]	2929579	1			T23	46		T24	593		T25	45
all_pins[5]	values[0x1]	1794581	1			T23	35		T24	275		T25	32
all_pins[5]	transitions[0x0=>0x1]	1074690	1			T23	15		T24	134		T25	15
all_pins[5]	transitions[0x1=>0x0]	1068314	1			T23	9		T24	226		T25	24
all_pins[6]	values[0x0]	2934154	1			T23	49		T24	528		T25	38
all_pins[6]	values[0x1]	1790006	1			T23	32		T24	340		T25	39
all_pins[6]	transitions[0x0=>0x1]	1071001	1			T23	19		T24	232		T25	20
all_pins[6]	transitions[0x1=>0x0]	1075576	1			T23	22		T24	167		T25	13
all_pins[7]	values[0x0]	2932508	1			T23	44		T24	538		T25	38
all_pins[7]	values[0x1]	1791652	1			T23	37		T24	330		T25	39
all_pins[7]	transitions[0x0=>0x1]	1071503	1			T23	20		T24	204		T25	16
all_pins[7]	transitions[0x1=>0x0]	1069857	1			T23	15		T24	214		T25	16
all_pins[8]	values[0x0]	2931418	1			T23	43		T24	495		T25	42
all_pins[8]	values[0x1]	1792742	1			T23	38		T24	373		T25	35
all_pins[8]	transitions[0x0=>0x1]	1072553	1			T23	21		T24	240		T25	16
all_pins[8]	transitions[0x1=>0x0]	1071463	1			T23	20		T24	197		T25	20
all_pins[9]	values[0x0]	2925260	1			T23	47		T24	498		T25	36
all_pins[9]	values[0x1]	1798900	1			T23	34		T24	370		T25	41
all_pins[9]	transitions[0x0=>0x1]	1074605	1			T23	15		T24	207		T25	22
all_pins[9]	transitions[0x1=>0x0]	1068447	1			T23	19		T24	210		T25	16
all_pins[10]	values[0x0]	2932122	1			T23	43		T24	519		T25	34
all_pins[10]	values[0x1]	1792038	1			T23	38		T24	349		T25	43
all_pins[10]	transitions[0x0=>0x1]	1071580	1			T23	16		T24	201		T25	20
all_pins[10]	transitions[0x1=>0x0]	1078442	1			T23	12		T24	222		T25	18
all_pins[11]	values[0x0]	2929932	1			T23	43		T24	513		T25	53
all_pins[11]	values[0x1]	1794228	1			T23	38		T24	355		T25	24
all_pins[11]	transitions[0x0=>0x1]	1074083	1			T23	19		T24	199		T25	9
all_pins[11]	transitions[0x1=>0x0]	1071893	1			T23	19		T24	193		T25	28
all_pins[12]	values[0x0]	2932320	1			T23	34		T24	579		T25	40
all_pins[12]	values[0x1]	1791840	1			T23	47		T24	289		T25	37
all_pins[12]	transitions[0x0=>0x1]	1068999	1			T23	24		T24	180		T25	25
all_pins[12]	transitions[0x1=>0x0]	1071387	1			T23	15		T24	246		T25	12
all_pins[13]	values[0x0]	2927483	1			T23	47		T24	599		T25	40
all_pins[13]	values[0x1]	1796677	1			T23	34		T24	269		T25	37
all_pins[13]	transitions[0x0=>0x1]	1075747	1			T23	13		T24	184		T25	18
all_pins[13]	transitions[0x1=>0x0]	1070910	1			T23	26		T24	204		T25	18
all_pins[14]	values[0x0]	2926882	1			T23	48		T24	494		T25	43
all_pins[14]	values[0x1]	1797278	1			T23	33		T24	374		T25	34
all_pins[14]	transitions[0x0=>0x1]	1072762	1			T23	15		T24	265		T25	20
all_pins[14]	transitions[0x1=>0x0]	1072161	1			T23	16		T24	160		T25	23
all_pins[15]	values[0x0]	2929412	1			T23	37		T24	498		T25	36
all_pins[15]	values[0x1]	1794748	1			T23	44		T24	370		T25	41
all_pins[15]	transitions[0x0=>0x1]	1071176	1			T23	27		T24	174		T25	21
all_pins[15]	transitions[0x1=>0x0]	1073706	1			T23	16		T24	178		T25	14
all_pins[16]	values[0x0]	2934764	1			T23	43		T24	499		T25	37
all_pins[16]	values[0x1]	1789396	1			T23	38		T24	369		T25	40
all_pins[16]	transitions[0x0=>0x1]	1069623	1			T23	16		T24	204		T25	20
all_pins[16]	transitions[0x1=>0x0]	1074975	1			T23	22		T24	205		T25	21
all_pins[17]	values[0x0]	2930859	1			T23	45		T24	540		T25	42
all_pins[17]	values[0x1]	1793301	1			T23	36		T24	328		T25	35
all_pins[17]	transitions[0x0=>0x1]	1073673	1			T23	20		T24	181		T25	19
all_pins[17]	transitions[0x1=>0x0]	1069768	1			T23	22		T24	222		T25	24
all_pins[18]	values[0x0]	2928038	1			T23	38		T24	523		T25	35
all_pins[18]	values[0x1]	1796122	1			T23	43		T24	345		T25	42
all_pins[18]	transitions[0x0=>0x1]	1071907	1			T23	23		T24	193		T25	23
all_pins[18]	transitions[0x1=>0x0]	1069086	1			T23	16		T24	176		T25	16
all_pins[19]	values[0x0]	2929595	1			T23	38		T24	453		T25	40
all_pins[19]	values[0x1]	1794565	1			T23	43		T24	415		T25	37
all_pins[19]	transitions[0x0=>0x1]	1072504	1			T23	17		T24	216		T25	19
all_pins[19]	transitions[0x1=>0x0]	1074061	1			T23	17		T24	146		T25	24
all_pins[20]	values[0x0]	2932033	1			T23	43		T24	532		T25	35
all_pins[20]	values[0x1]	1792127	1			T23	38		T24	336		T25	42
all_pins[20]	transitions[0x0=>0x1]	1070413	1			T23	16		T24	131		T25	23
all_pins[20]	transitions[0x1=>0x0]	1072851	1			T23	21		T24	210		T25	18
all_pins[21]	values[0x0]	2923749	1			T23	48		T24	606		T25	44
all_pins[21]	values[0x1]	1800411	1			T23	33		T24	262		T25	33
all_pins[21]	transitions[0x0=>0x1]	1077432	1			T23	19		T24	187		T25	13
all_pins[21]	transitions[0x1=>0x0]	1069148	1			T23	24		T24	261		T25	22
all_pins[22]	values[0x0]	2935700	1			T23	45		T24	479		T25	41
all_pins[22]	values[0x1]	1788460	1			T23	36		T24	389		T25	36
all_pins[22]	transitions[0x0=>0x1]	1066471	1			T23	24		T24	263		T25	22
all_pins[22]	transitions[0x1=>0x0]	1078422	1			T23	21		T24	136		T25	19
all_pins[23]	values[0x0]	2936915	1			T23	46		T24	572		T25	44
all_pins[23]	values[0x1]	1787245	1			T23	35		T24	296		T25	33
all_pins[23]	transitions[0x0=>0x1]	1070314	1			T23	20		T24	172		T25	13
all_pins[23]	transitions[0x1=>0x0]	1071529	1			T23	21		T24	265		T25	16
all_pins[24]	values[0x0]	2930915	1			T23	46		T24	586		T25	38
all_pins[24]	values[0x1]	1793245	1			T23	35		T24	282		T25	39
all_pins[24]	transitions[0x0=>0x1]	1075240	1			T23	22		T24	182		T25	18
all_pins[24]	transitions[0x1=>0x0]	1069240	1			T23	22		T24	196		T25	12
all_pins[25]	values[0x0]	2935920	1			T23	39		T24	435		T25	42
all_pins[25]	values[0x1]	1788240	1			T23	42		T24	433		T25	35
all_pins[25]	transitions[0x0=>0x1]	1069525	1			T23	23		T24	268		T25	16
all_pins[25]	transitions[0x1=>0x0]	1074530	1			T23	16		T24	117		T25	20
all_pins[26]	values[0x0]	2934541	1			T23	49		T24	561		T25	37
all_pins[26]	values[0x1]	1789619	1			T23	32		T24	307		T25	40
all_pins[26]	transitions[0x0=>0x1]	1070200	1			T23	16		T24	160		T25	21
all_pins[26]	transitions[0x1=>0x0]	1068821	1			T23	26		T24	286		T25	16
all_pins[27]	values[0x0]	2930074	1			T23	42		T24	520		T25	39
all_pins[27]	values[0x1]	1794086	1			T23	39		T24	348		T25	38
all_pins[27]	transitions[0x0=>0x1]	1072791	1			T23	23		T24	198		T25	17
all_pins[27]	transitions[0x1=>0x0]	1068324	1			T23	16		T24	157		T25	19
all_pins[28]	values[0x0]	2930938	1			T23	41		T24	566		T25	47
all_pins[28]	values[0x1]	1793222	1			T23	40		T24	302		T25	30
all_pins[28]	transitions[0x0=>0x1]	1071917	1			T23	22		T24	209		T25	18
all_pins[28]	transitions[0x1=>0x0]	1072781	1			T23	21		T24	255		T25	26
all_pins[29]	values[0x0]	2933000	1			T23	38		T24	543		T25	41
all_pins[29]	values[0x1]	1791160	1			T23	43		T24	325		T25	36
all_pins[29]	transitions[0x0=>0x1]	1070807	1			T23	22		T24	201		T25	23
all_pins[29]	transitions[0x1=>0x0]	1072869	1			T23	19		T24	178		T25	17
all_pins[30]	values[0x0]	2936755	1			T23	35		T24	604		T25	37
all_pins[30]	values[0x1]	1787405	1			T23	46		T24	264		T25	40
all_pins[30]	transitions[0x0=>0x1]	1071719	1			T23	21		T24	133		T25	19
all_pins[30]	transitions[0x1=>0x0]	1075474	1			T23	18		T24	194		T25	15
all_pins[31]	values[0x0]	2926931	1			T23	37		T24	526		T25	40
all_pins[31]	values[0x1]	1797229	1			T23	44		T24	342		T25	37
all_pins[31]	transitions[0x0=>0x1]	1076513	1			T23	19		T24	261		T25	18
all_pins[31]	transitions[0x1=>0x0]	1066689	1			T23	21		T24	183		T25	21