Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[1]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[2]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[3]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[4]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[5]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[6]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[7]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[8]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[9]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[10]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[11]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[12]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[13]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[14]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[15]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[16]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[17]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[18]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[19]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[20]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[21]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[22]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[23]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[24]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[25]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[26]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[27]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[28]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[29]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[30]	15827605	1			T23	38182		T24	2939		T25	1259
all_values[31]	15827605	1			T23	38182		T24	2939		T25	1259

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

290901867

1

T23

122182

T24

47150

T25

40288

auto[1]

215581493

1

T24

46898

T30

292

T32

12771

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116631200

1

T23

122182

T24

6924

T25

40288

auto[1]

389852160

1

T24

87124

T30

591

T32

22749

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

500996656

1

T23

122182

T24

94048

T25

40288

auto[1]

5486704

1

T30

66

T32

924

T44

331

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3002524	1			T23	38182		T24	112		T25	1259
all_values[0]	auto[0]	auto[0]	auto[1]	6006054	1			T24	1157		T30	7		T32	368
all_values[0]	auto[0]	auto[1]	auto[0]	649289	1			T24	124		T30	9		T32	53
all_values[0]	auto[0]	auto[1]	auto[1]	5998410	1			T24	1546		T30	2		T32	296
all_values[0]	auto[1]	auto[0]	auto[1]	85771	1			T30	1		T32	15		T44	10
all_values[0]	auto[1]	auto[1]	auto[1]	85557	1			T30	1		T32	10		T44	3
all_values[1]	auto[0]	auto[0]	auto[0]	3001384	1			T23	38182		T24	106		T25	1259
all_values[1]	auto[0]	auto[0]	auto[1]	5967503	1			T24	1185		T30	5		T32	281
all_values[1]	auto[0]	auto[1]	auto[0]	647122	1			T24	128		T32	118		T113	32
all_values[1]	auto[0]	auto[1]	auto[1]	6040255	1			T24	1520		T32	341		T113	181
all_values[1]	auto[1]	auto[0]	auto[1]	86500	1			T30	2		T32	13		T44	9
all_values[1]	auto[1]	auto[1]	auto[1]	84841	1			T32	16		T44	1		T55	530
all_values[2]	auto[0]	auto[0]	auto[0]	2995670	1			T23	38182		T24	120		T25	1259
all_values[2]	auto[0]	auto[0]	auto[1]	6004687	1			T24	1259		T30	16		T32	276
all_values[2]	auto[0]	auto[1]	auto[0]	646782	1			T24	84		T32	50		T113	51
all_values[2]	auto[0]	auto[1]	auto[1]	6009505	1			T24	1476		T32	399		T113	173
all_values[2]	auto[1]	auto[0]	auto[1]	85485	1			T30	2		T32	10		T44	9
all_values[2]	auto[1]	auto[1]	auto[1]	85476	1			T32	18		T44	5		T55	500
all_values[3]	auto[0]	auto[0]	auto[0]	2997571	1			T23	38182		T24	101		T25	1259
all_values[3]	auto[0]	auto[0]	auto[1]	6037193	1			T24	1652		T30	6		T32	296
all_values[3]	auto[0]	auto[1]	auto[0]	646558	1			T24	87		T30	10		T32	51
all_values[3]	auto[0]	auto[1]	auto[1]	5974928	1			T24	1099		T30	11		T32	353
all_values[3]	auto[1]	auto[0]	auto[1]	85863	1			T32	15		T44	3		T55	477
all_values[3]	auto[1]	auto[1]	auto[1]	85492	1			T32	18		T44	5		T55	516
all_values[4]	auto[0]	auto[0]	auto[0]	2995583	1			T23	38182		T24	67		T25	1259
all_values[4]	auto[0]	auto[0]	auto[1]	6011376	1			T24	1170		T30	2		T32	369
all_values[4]	auto[0]	auto[1]	auto[0]	641286	1			T24	182		T30	10		T32	51
all_values[4]	auto[0]	auto[1]	auto[1]	6008340	1			T24	1520		T30	10		T32	257
all_values[4]	auto[1]	auto[0]	auto[1]	85820	1			T32	17		T44	5		T55	495
all_values[4]	auto[1]	auto[1]	auto[1]	85200	1			T30	1		T32	10		T44	3
all_values[5]	auto[0]	auto[0]	auto[0]	2999420	1			T23	38182		T24	187		T25	1259
all_values[5]	auto[0]	auto[0]	auto[1]	6010224	1			T24	1604		T30	20		T32	338
all_values[5]	auto[0]	auto[1]	auto[0]	648327	1			T24	117		T32	20		T113	33
all_values[5]	auto[0]	auto[1]	auto[1]	5998031	1			T24	1031		T32	376		T113	91
all_values[5]	auto[1]	auto[0]	auto[1]	86311	1			T30	2		T32	15		T44	4
all_values[5]	auto[1]	auto[1]	auto[1]	85292	1			T32	11		T44	5		T55	526
all_values[6]	auto[0]	auto[0]	auto[0]	2999822	1			T23	38182		T24	130		T25	1259
all_values[6]	auto[0]	auto[0]	auto[1]	6010132	1			T24	1226		T30	12		T32	340
all_values[6]	auto[0]	auto[1]	auto[0]	650083	1			T24	150		T30	5		T32	106
all_values[6]	auto[0]	auto[1]	auto[1]	5996150	1			T24	1433		T32	317		T113	147
all_values[6]	auto[1]	auto[0]	auto[1]	85445	1			T30	2		T32	11		T44	9
all_values[6]	auto[1]	auto[1]	auto[1]	85973	1			T32	15		T44	3		T55	504
all_values[7]	auto[0]	auto[0]	auto[0]	2997864	1			T23	38182		T24	164		T25	1259
all_values[7]	auto[0]	auto[0]	auto[1]	6008357	1			T24	1370		T30	8		T32	394
all_values[7]	auto[0]	auto[1]	auto[0]	635559	1			T24	119		T30	4		T32	24
all_values[7]	auto[0]	auto[1]	auto[1]	6014676	1			T24	1286		T30	16		T32	314
all_values[7]	auto[1]	auto[0]	auto[1]	86146	1			T30	1		T32	21		T44	6
all_values[7]	auto[1]	auto[1]	auto[1]	85003	1			T30	1		T32	10		T44	5
all_values[8]	auto[0]	auto[0]	auto[0]	3000187	1			T23	38182		T24	119		T25	1259
all_values[8]	auto[0]	auto[0]	auto[1]	6007936	1			T24	1197		T30	6		T32	341
all_values[8]	auto[0]	auto[1]	auto[0]	645691	1			T24	130		T30	5		T32	62
all_values[8]	auto[0]	auto[1]	auto[1]	6002085	1			T24	1493		T30	9		T32	338
all_values[8]	auto[1]	auto[0]	auto[1]	86882	1			T30	1		T32	13		T44	6
all_values[8]	auto[1]	auto[1]	auto[1]	84824	1			T32	13		T44	5		T55	537
all_values[9]	auto[0]	auto[0]	auto[0]	2995491	1			T23	38182		T24	98		T25	1259
all_values[9]	auto[0]	auto[0]	auto[1]	6011491	1			T24	1232		T30	7		T32	332
all_values[9]	auto[0]	auto[1]	auto[0]	652116	1			T24	94		T30	10		T32	46
all_values[9]	auto[0]	auto[1]	auto[1]	5996615	1			T24	1515		T30	6		T32	326
all_values[9]	auto[1]	auto[0]	auto[1]	85929	1			T30	2		T32	13		T44	8
all_values[9]	auto[1]	auto[1]	auto[1]	85963	1			T32	11		T44	3		T55	522
all_values[10]	auto[0]	auto[0]	auto[0]	2996234	1			T23	38182		T24	75		T25	1259
all_values[10]	auto[0]	auto[0]	auto[1]	6026294	1			T24	1361		T30	7		T32	281
all_values[10]	auto[0]	auto[1]	auto[0]	639889	1			T24	112		T32	18		T113	31
all_values[10]	auto[0]	auto[1]	auto[1]	5994057	1			T24	1391		T32	445		T113	177
all_values[10]	auto[1]	auto[0]	auto[1]	86222	1			T30	2		T32	13		T44	4
all_values[10]	auto[1]	auto[1]	auto[1]	84909	1			T32	17		T44	5		T55	491
all_values[11]	auto[0]	auto[0]	auto[0]	3004110	1			T23	38182		T24	92		T25	1259
all_values[11]	auto[0]	auto[0]	auto[1]	5971568	1			T24	1356		T30	18		T32	368
all_values[11]	auto[0]	auto[1]	auto[0]	652965	1			T24	81		T32	52		T113	26
all_values[11]	auto[0]	auto[1]	auto[1]	6027900	1			T24	1410		T32	324		T113	180
all_values[11]	auto[1]	auto[0]	auto[1]	86144	1			T30	3		T32	19		T44	7
all_values[11]	auto[1]	auto[1]	auto[1]	84918	1			T32	17		T44	5		T55	490
all_values[12]	auto[0]	auto[0]	auto[0]	2997645	1			T23	38182		T24	94		T25	1259
all_values[12]	auto[0]	auto[0]	auto[1]	5990743	1			T24	1642		T30	8		T32	376
all_values[12]	auto[0]	auto[1]	auto[0]	646020	1			T24	41		T30	5		T32	45
all_values[12]	auto[0]	auto[1]	auto[1]	6021367	1			T24	1162		T30	9		T32	309
all_values[12]	auto[1]	auto[0]	auto[1]	86009	1			T30	1		T32	13		T44	9
all_values[12]	auto[1]	auto[1]	auto[1]	85821	1			T32	14		T44	2		T55	557
all_values[13]	auto[0]	auto[0]	auto[0]	2991824	1			T23	38182		T24	103		T25	1259
all_values[13]	auto[0]	auto[0]	auto[1]	5989227	1			T24	1633		T30	12		T32	298
all_values[13]	auto[0]	auto[1]	auto[0]	660210	1			T24	115		T30	1		T32	83
all_values[13]	auto[0]	auto[1]	auto[1]	6014784	1			T24	1088		T30	4		T32	342
all_values[13]	auto[1]	auto[0]	auto[1]	85305	1			T32	21		T44	6		T55	529
all_values[13]	auto[1]	auto[1]	auto[1]	86255	1			T32	17		T44	6		T55	495
all_values[14]	auto[0]	auto[0]	auto[0]	2990557	1			T23	38182		T24	113		T25	1259
all_values[14]	auto[0]	auto[0]	auto[1]	6001504	1			T24	1246		T30	22		T32	362
all_values[14]	auto[0]	auto[1]	auto[0]	639217	1			T24	88		T32	57		T113	49
all_values[14]	auto[0]	auto[1]	auto[1]	6024979	1			T24	1492		T32	277		T113	190
all_values[14]	auto[1]	auto[0]	auto[1]	85789	1			T30	2		T32	18		T44	7
all_values[14]	auto[1]	auto[1]	auto[1]	85559	1			T32	16		T44	3		T55	521
all_values[15]	auto[0]	auto[0]	auto[0]	2994248	1			T23	38182		T24	89		T25	1259
all_values[15]	auto[0]	auto[0]	auto[1]	6015586	1			T24	1129		T30	14		T32	444
all_values[15]	auto[0]	auto[1]	auto[0]	646621	1			T24	143		T32	32		T113	23
all_values[15]	auto[0]	auto[1]	auto[1]	5999541	1			T24	1578		T30	9		T32	243
all_values[15]	auto[1]	auto[0]	auto[1]	85979	1			T30	1		T32	21		T44	6
all_values[15]	auto[1]	auto[1]	auto[1]	85630	1			T32	14		T44	4		T55	520
all_values[16]	auto[0]	auto[0]	auto[0]	2996470	1			T23	38182		T24	62		T25	1259
all_values[16]	auto[0]	auto[0]	auto[1]	6017174	1			T24	1255		T30	6		T32	335
all_values[16]	auto[0]	auto[1]	auto[0]	648703	1			T24	171		T30	4		T32	28
all_values[16]	auto[0]	auto[1]	auto[1]	5993826	1			T24	1451		T30	12		T32	415
all_values[16]	auto[1]	auto[0]	auto[1]	85632	1			T30	2		T32	9		T44	3
all_values[16]	auto[1]	auto[1]	auto[1]	85800	1			T32	15		T44	3		T55	491
all_values[17]	auto[0]	auto[0]	auto[0]	2996850	1			T23	38182		T24	61		T25	1259
all_values[17]	auto[0]	auto[0]	auto[1]	6026003	1			T24	1395		T30	14		T32	341
all_values[17]	auto[0]	auto[1]	auto[0]	652912	1			T24	133		T30	5		T32	49
all_values[17]	auto[0]	auto[1]	auto[1]	5980169	1			T24	1350		T32	372		T113	207
all_values[17]	auto[1]	auto[0]	auto[1]	86735	1			T30	3		T32	10		T44	9
all_values[17]	auto[1]	auto[1]	auto[1]	84936	1			T32	14		T44	4		T55	534
all_values[18]	auto[0]	auto[0]	auto[0]	3000868	1			T23	38182		T24	83		T25	1259
all_values[18]	auto[0]	auto[0]	auto[1]	5986086	1			T24	1438		T30	10		T32	292
all_values[18]	auto[0]	auto[1]	auto[0]	649091	1			T24	78		T30	7		T32	28
all_values[18]	auto[0]	auto[1]	auto[1]	6020400	1			T24	1340		T32	450		T113	157
all_values[18]	auto[1]	auto[0]	auto[1]	85859	1			T30	1		T32	13		T44	5
all_values[18]	auto[1]	auto[1]	auto[1]	85301	1			T32	18		T44	4		T55	539
all_values[19]	auto[0]	auto[0]	auto[0]	2995309	1			T23	38182		T24	78		T25	1259
all_values[19]	auto[0]	auto[0]	auto[1]	6030695	1			T24	1284		T30	15		T32	409
all_values[19]	auto[0]	auto[1]	auto[0]	643529	1			T24	59		T30	1		T32	13
all_values[19]	auto[0]	auto[1]	auto[1]	5986683	1			T24	1518		T30	3		T32	305
all_values[19]	auto[1]	auto[0]	auto[1]	86182	1			T30	2		T32	17		T44	8
all_values[19]	auto[1]	auto[1]	auto[1]	85207	1			T30	1		T32	11		T44	3
all_values[20]	auto[0]	auto[0]	auto[0]	3003346	1			T23	38182		T24	145		T25	1259
all_values[20]	auto[0]	auto[0]	auto[1]	5995492	1			T24	1277		T30	8		T32	375
all_values[20]	auto[0]	auto[1]	auto[0]	646067	1			T24	140		T30	3		T32	75
all_values[20]	auto[0]	auto[1]	auto[1]	6011316	1			T24	1377		T30	12		T32	294
all_values[20]	auto[1]	auto[0]	auto[1]	86146	1			T30	3		T32	9		T44	7
all_values[20]	auto[1]	auto[1]	auto[1]	85238	1			T30	1		T32	12		T44	3
all_values[21]	auto[0]	auto[0]	auto[0]	2992312	1			T23	38182		T24	212		T25	1259
all_values[21]	auto[0]	auto[0]	auto[1]	5980656	1			T24	1493		T30	16		T32	344
all_values[21]	auto[0]	auto[1]	auto[0]	653079	1			T24	107		T30	5		T32	56
all_values[21]	auto[0]	auto[1]	auto[1]	6029894	1			T24	1127		T32	319		T113	158
all_values[21]	auto[1]	auto[0]	auto[1]	85833	1			T30	2		T32	13		T44	5
all_values[21]	auto[1]	auto[1]	auto[1]	85831	1			T32	20		T44	6		T55	538
all_values[22]	auto[0]	auto[0]	auto[0]	2998751	1			T23	38182		T24	128		T25	1259
all_values[22]	auto[0]	auto[0]	auto[1]	6035056	1			T24	1121		T30	14		T32	350
all_values[22]	auto[0]	auto[1]	auto[0]	650346	1			T24	82		T30	1		T32	47
all_values[22]	auto[0]	auto[1]	auto[1]	5971663	1			T24	1608		T30	3		T32	331
all_values[22]	auto[1]	auto[0]	auto[1]	85416	1			T30	1		T32	10		T44	6
all_values[22]	auto[1]	auto[1]	auto[1]	86373	1			T30	1		T32	17		T44	4
all_values[23]	auto[0]	auto[0]	auto[0]	3007375	1			T23	38182		T24	125		T25	1259
all_values[23]	auto[0]	auto[0]	auto[1]	6025719	1			T24	1392		T30	9		T32	334
all_values[23]	auto[0]	auto[1]	auto[0]	635393	1			T24	144		T30	2		T32	46
all_values[23]	auto[0]	auto[1]	auto[1]	5987768	1			T24	1278		T30	7		T32	349
all_values[23]	auto[1]	auto[0]	auto[1]	86019	1			T30	2		T32	18		T44	7
all_values[23]	auto[1]	auto[1]	auto[1]	85331	1			T32	13		T44	4		T55	482
all_values[24]	auto[0]	auto[0]	auto[0]	2998976	1			T23	38182		T24	84		T25	1259
all_values[24]	auto[0]	auto[0]	auto[1]	6032968	1			T24	1664		T30	5		T32	303
all_values[24]	auto[0]	auto[1]	auto[0]	642401	1			T24	47		T30	1		T32	116
all_values[24]	auto[0]	auto[1]	auto[1]	5981678	1			T24	1144		T30	12		T32	321
all_values[24]	auto[1]	auto[0]	auto[1]	85984	1			T30	3		T32	15		T44	9
all_values[24]	auto[1]	auto[1]	auto[1]	85598	1			T30	1		T32	19		T44	1
all_values[25]	auto[0]	auto[0]	auto[0]	2996750	1			T23	38182		T24	54		T25	1259
all_values[25]	auto[0]	auto[0]	auto[1]	5997079	1			T24	1201		T30	5		T32	363
all_values[25]	auto[0]	auto[1]	auto[0]	641433	1			T24	76		T32	42		T113	39
all_values[25]	auto[0]	auto[1]	auto[1]	6021471	1			T24	1608		T30	9		T32	344
all_values[25]	auto[1]	auto[0]	auto[1]	85452	1			T30	2		T32	9		T44	5
all_values[25]	auto[1]	auto[1]	auto[1]	85420	1			T32	13		T44	3		T55	489
all_values[26]	auto[0]	auto[0]	auto[0]	3002140	1			T23	38182		T24	159		T25	1259
all_values[26]	auto[0]	auto[0]	auto[1]	5989300	1			T24	1447		T30	9		T32	305
all_values[26]	auto[0]	auto[1]	auto[0]	642012	1			T24	59		T30	2		T32	51
all_values[26]	auto[0]	auto[1]	auto[1]	6022951	1			T24	1274		T30	11		T32	396
all_values[26]	auto[1]	auto[0]	auto[1]	85656	1			T30	3		T32	11		T44	3
all_values[26]	auto[1]	auto[1]	auto[1]	85546	1			T30	1		T32	20		T44	5
all_values[27]	auto[0]	auto[0]	auto[0]	3002504	1			T23	38182		T24	94		T25	1259
all_values[27]	auto[0]	auto[0]	auto[1]	5989102	1			T24	1320		T30	16		T32	317
all_values[27]	auto[0]	auto[1]	auto[0]	643549	1			T24	83		T32	65		T113	62
all_values[27]	auto[0]	auto[1]	auto[1]	6020461	1			T24	1442		T30	7		T32	349
all_values[27]	auto[1]	auto[0]	auto[1]	86138	1			T30	2		T32	19		T44	6
all_values[27]	auto[1]	auto[1]	auto[1]	85851	1			T32	11		T44	5		T55	543
all_values[28]	auto[0]	auto[0]	auto[0]	3006137	1			T23	38182		T24	152		T25	1259
all_values[28]	auto[0]	auto[0]	auto[1]	5996725	1			T24	1549		T30	6		T32	450
all_values[28]	auto[0]	auto[1]	auto[0]	638883	1			T24	66		T32	14		T113	2
all_values[28]	auto[0]	auto[1]	auto[1]	6013951	1			T24	1172		T30	9		T32	254
all_values[28]	auto[1]	auto[0]	auto[1]	85901	1			T30	3		T32	17		T44	9
all_values[28]	auto[1]	auto[1]	auto[1]	86008	1			T32	9		T44	3		T55	553
all_values[29]	auto[0]	auto[0]	auto[0]	3014506	1			T23	38182		T24	107		T25	1259
all_values[29]	auto[0]	auto[0]	auto[1]	6008503	1			T24	1302		T30	14		T32	405
all_values[29]	auto[0]	auto[1]	auto[0]	644325	1			T24	138		T30	2		T32	61
all_values[29]	auto[0]	auto[1]	auto[1]	5988874	1			T24	1392		T30	9		T32	282
all_values[29]	auto[1]	auto[0]	auto[1]	86078	1			T30	2		T32	11		T44	6
all_values[29]	auto[1]	auto[1]	auto[1]	85319	1			T30	1		T32	16		T44	2
all_values[30]	auto[0]	auto[0]	auto[0]	2991598	1			T23	38182		T24	147		T25	1259
all_values[30]	auto[0]	auto[0]	auto[1]	6022394	1			T24	1548		T30	19		T32	293
all_values[30]	auto[0]	auto[1]	auto[0]	645265	1			T24	153		T32	31		T113	65
all_values[30]	auto[0]	auto[1]	auto[1]	5996354	1			T24	1091		T32	431		T113	202
all_values[30]	auto[1]	auto[0]	auto[1]	86963	1			T30	1		T32	11		T44	7
all_values[30]	auto[1]	auto[1]	auto[1]	85031	1			T32	21		T44	5		T55	519
all_values[31]	auto[0]	auto[0]	auto[0]	2997595	1			T23	38182		T24	58		T25	1259
all_values[31]	auto[0]	auto[0]	auto[1]	5985701	1			T24	1526		T30	5		T32	468
all_values[31]	auto[0]	auto[1]	auto[0]	644856	1			T24	74		T30	5		T32	39
all_values[31]	auto[0]	auto[1]	auto[1]	6027846	1			T24	1281		T30	14		T32	208
all_values[31]	auto[1]	auto[0]	auto[1]	86124	1			T30	1		T32	19		T44	8
all_values[31]	auto[1]	auto[1]	auto[1]	85483	1			T30	2		T32	9		T44	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal