Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[1]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[2]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[3]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[4]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[5]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[6]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[7]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[8]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[9]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[10]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[11]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[12]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[13]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[14]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[15]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[16]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[17]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[18]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[19]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[20]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[21]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[22]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[23]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[24]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[25]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[26]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[27]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[28]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[29]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[30]	15572965	1			T23	38182		T24	2322		T25	1259
bins_for_gpio_bits[31]	15572965	1			T23	38182		T24	2322		T25	1259

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299803664

1

T23

613362

T24

37067

T25

20023

auto[1]

198531216

1

T23

608462

T24

37237

T25

20265

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

400920383

1

T23

122182

T24

74304

T25

40288

auto[1]

97414497

1

T27

12007

T28

6378

T29

624

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

371754813

1

T23

122182

T24

74304

T25

40288

auto[1]

126580067

1

T27

11884

T28

12991

T29

1583

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5825906	1			T23	19410		T24	1227		T25	584
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4250585	1			T23	18772		T24	1095		T25	675
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1536011	1			T27	172		T28	95		T29	4
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1994008	1			T27	191		T28	214		T29	7
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	445357	1			T28	36		T29	27		T30	8
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1521098	1			T27	188		T28	112		T29	7
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5838134	1			T23	17966		T24	1156		T25	622
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4248340	1			T23	20216		T24	1166		T25	637
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1533792	1			T27	182		T28	159		T30	7
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1992521	1			T27	209		T28	193		T29	2
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	444983	1			T28	40		T29	34		T30	7
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1515195	1			T27	190		T28	118		T29	3
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5849080	1			T23	17915		T24	1170		T25	657
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4242735	1			T23	20267		T24	1152		T25	602
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1524518	1			T27	214		T28	82		T29	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1992615	1			T27	166		T28	211		T29	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	444960	1			T28	26		T29	54		T30	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1519057	1			T27	166		T28	126		T29	4
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5855562	1			T23	21018		T24	1122		T25	687
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4232350	1			T23	17164		T24	1200		T25	572
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1536582	1			T27	208		T28	73		T29	5
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1987258	1			T27	167		T28	280		T29	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	445616	1			T28	31		T29	26		T30	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1515597	1			T27	232		T28	114		T29	6
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5847281	1			T23	19212		T24	1152		T25	611
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4237931	1			T23	18970		T24	1170		T25	648
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1528340	1			T27	192		T28	80		T29	12
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1997487	1			T27	174		T28	299		T29	3
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	445471	1			T28	46		T29	27		T30	8
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1516455	1			T27	221		T28	96		T30	2
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5851493	1			T23	20562		T24	1149		T25	597
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4236169	1			T23	17620		T24	1173		T25	662
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1533546	1			T27	187		T28	98		T29	7
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1988697	1			T27	182		T28	302		T29	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	443554	1			T28	47		T29	30		T30	22
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1519506	1			T27	194		T28	78		T29	4
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5834968	1			T23	19036		T24	1169		T25	687
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4244521	1			T23	19146		T24	1153		T25	572
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1527104	1			T27	238		T28	125		T29	16
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1997036	1			T27	148		T28	215		T29	6
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	445858	1			T28	33		T29	45		T30	6
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1523478	1			T27	147		T28	130		T29	4
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5840020	1			T23	17827		T24	1157		T25	626
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4253744	1			T23	20355		T24	1165		T25	633
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1538624	1			T27	155		T28	107		T29	9
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1986636	1			T27	198		T28	277		T29	7
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	441653	1			T28	36		T29	40		T30	12
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1512288	1			T27	230		T28	58		T29	9
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5845931	1			T23	20266		T24	1147		T25	513
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4237656	1			T23	17916		T24	1175		T25	746
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1535038	1			T27	173		T28	121		T29	14
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1993744	1			T27	152		T28	319		T29	1
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	443567	1			T28	42		T29	42		T30	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1517029	1			T27	232		T28	77		T29	2
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5833512	1			T23	19735		T24	1152		T25	669
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4247613	1			T23	18447		T24	1170		T25	590
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1529946	1			T27	204		T28	75		T29	7
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1997830	1			T27	171		T28	307		T29	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	446564	1			T28	47		T29	37		T30	2
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1517500	1			T27	176		T28	125		T29	19
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5844069	1			T23	18358		T24	1149		T25	643
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4241212	1			T23	19824		T24	1173		T25	616
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1530221	1			T27	246		T28	117		T29	18
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1992008	1			T27	153		T28	302		T29	5
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	444762	1			T28	47		T29	36		T30	15
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1520693	1			T27	162		T28	109		T29	6
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5853230	1			T23	19267		T24	1134		T25	700
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4234104	1			T23	18915		T24	1188		T25	559
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1527310	1			T27	194		T28	105		T29	4
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1995392	1			T27	170		T28	318		T29	8
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	446272	1			T28	42		T29	48		T30	8
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1516657	1			T27	182		T28	81		T29	18
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5847435	1			T23	18390		T24	1161		T25	700
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4243084	1			T23	19792		T24	1161		T25	559
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1529717	1			T27	192		T28	149		T29	13
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1993234	1			T27	182		T28	243		T29	5
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	444243	1			T28	30		T29	49		T30	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1515252	1			T27	153		T28	77		T29	7
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5840553	1			T23	20221		T24	1151		T25	547
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4243054	1			T23	17961		T24	1171		T25	712
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1532094	1			T27	168		T28	133		T29	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1995898	1			T27	232		T28	241		T29	5
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	444131	1			T28	29		T29	30		T30	11
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1517235	1			T27	168		T28	121		T29	15
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5846112	1			T23	19823		T24	1181		T25	576
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4243076	1			T23	18359		T24	1141		T25	683
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1534833	1			T27	166		T28	88		T29	22
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1993493	1			T27	210		T28	345		T29	2
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	442684	1			T28	40		T29	16		T31	86
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1512767	1			T27	206		T28	109		T29	9
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5850541	1			T23	19359		T24	1158		T25	615
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4233710	1			T23	18823		T24	1164		T25	644
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1532617	1			T27	184		T28	112		T29	17
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1992523	1			T27	187		T28	272		T29	5
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	445461	1			T28	42		T29	21		T30	6
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1518113	1			T27	208		T28	116		T29	10
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5850451	1			T23	19477		T24	1199		T25	606
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4246465	1			T23	18705		T24	1123		T25	653
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1525294	1			T27	164		T28	83		T29	21
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1995326	1			T27	223		T28	265		T29	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	443974	1			T28	20		T29	8		T30	20
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1511455	1			T27	164		T28	67		T29	17
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5828829	1			T23	18084		T24	1135		T25	530
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4255370	1			T23	20098		T24	1187		T25	729
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1526310	1			T27	148		T28	71		T29	20
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2001331	1			T27	222		T28	315		T29	5
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	444991	1			T28	34		T29	13		T30	9
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1516134	1			T27	173		T28	66		T29	12
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5844925	1			T23	19692		T24	1149		T25	614
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4250187	1			T23	18490		T24	1173		T25	645
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1520622	1			T27	202		T28	103		T29	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2001288	1			T27	173		T28	325		T29	10
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	446197	1			T28	49		T29	59		T30	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1509746	1			T27	182		T28	74		T29	16
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5846085	1			T23	18926		T24	1153		T25	664
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4245736	1			T23	19256		T24	1169		T25	595
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1522815	1			T27	225		T28	83		T29	17
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1995906	1			T27	140		T28	243		T29	4
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	445994	1			T28	32		T29	32		T31	113
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1516429	1			T27	164		T28	122		T29	12
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5848869	1			T23	19516		T24	1180		T25	639
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4245653	1			T23	18666		T24	1142		T25	620
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1528681	1			T27	181		T28	161		T29	4
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1994992	1			T27	164		T28	182		T29	3
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	440568	1			T28	26		T29	54		T30	13
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1514202	1			T27	168		T28	101		T29	23
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5838465	1			T23	18088		T24	1170		T25	654
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4243088	1			T23	20094		T24	1152		T25	605
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1526623	1			T27	209		T28	108		T29	9
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2000378	1			T27	152		T28	243		T29	5
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	445711	1			T28	25		T29	49		T30	6
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1518700	1			T27	172		T28	104		T29	4
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5844655	1			T23	19324		T24	1166		T25	643
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4246890	1			T23	18858		T24	1156		T25	616
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1527998	1			T27	199		T28	96		T29	8
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1994746	1			T27	194		T28	272		T29	7
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	443970	1			T28	42		T29	45		T30	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1514706	1			T27	170		T28	92		T29	11
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5840308	1			T23	18567		T24	1136		T25	626
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4250138	1			T23	19615		T24	1186		T25	633
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1528215	1			T27	153		T28	92		T29	9
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1995095	1			T27	192		T28	290		T29	3
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	446741	1			T28	30		T29	35		T30	10
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1512468	1			T27	208		T28	83		T29	15
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5841464	1			T23	20143		T24	1121		T25	622
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4252006	1			T23	18039		T24	1201		T25	637
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1528217	1			T27	162		T28	80		T29	15
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1993361	1			T27	214		T28	270		T29	6
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	443486	1			T28	32		T29	38		T30	19
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1514431	1			T27	198		T28	99		T29	7
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5848081	1			T23	18653		T24	1154		T25	606
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4237906	1			T23	19529		T24	1168		T25	653
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1527241	1			T27	200		T28	97		T29	9
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2001760	1			T27	172		T28	211		T29	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	447496	1			T28	23		T29	39		T30	9
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1510481	1			T27	188		T28	116		T29	2
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5856054	1			T23	18289		T24	1178		T25	664
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4234028	1			T23	19893		T24	1144		T25	595
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1526685	1			T27	176		T28	81		T29	6
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1998421	1			T27	195		T28	338		T29	3
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	446398	1			T28	60		T29	16		T31	111
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1511379	1			T27	184		T28	120		T29	16
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5849512	1			T23	17878		T24	1160		T25	548
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4243023	1			T23	20304		T24	1162		T25	711
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1520610	1			T27	172		T28	81		T31	4
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1998902	1			T27	184		T28	244		T29	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	446814	1			T28	39		T29	44		T30	8
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1514104	1			T27	212		T28	138		T29	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5853687	1			T23	20180		T24	1165		T25	652
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4241418	1			T23	18002		T24	1157		T25	607
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1523835	1			T27	204		T28	98		T29	5
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1994315	1			T27	198		T28	261		T30	32
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	441805	1			T28	27		T29	37		T30	5
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1517905	1			T27	185		T28	100		T29	8
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5844052	1			T23	19142		T24	1211		T25	605
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4247515	1			T23	19040		T24	1111		T25	654
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1526885	1			T27	182		T28	75		T29	9
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1999827	1			T27	156		T28	307		T29	8
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	443101	1			T28	39		T29	58		T30	6
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1511585	1			T27	191		T28	56		T29	11
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5843004	1			T23	18919		T24	1155		T25	641
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4244321	1			T23	19263		T24	1167		T25	618
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1522463	1			T27	177		T28	88		T29	26
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2002068	1			T27	196		T28	279		T29	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	447971	1			T28	28		T29	24		T30	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1513138	1			T27	216		T28	66		T29	8
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5842463	1			T23	20119		T24	1100		T25	675
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4251058	1			T23	18063		T24	1222		T25	584
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1532609	1			T27	180		T28	96		T29	10
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1995441	1			T27	219		T28	295		T29	6
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	447076	1			T28	27		T29	37		T30	14
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1504318	1			T27	168		T28	115		T29	9

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal