Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9094349 |
1 |
|
|
T23 |
38182 |
|
T24 |
1269 |
|
T25 |
1259 |
| auto[1] |
6733256 |
1 |
|
|
T24 |
1670 |
|
T30 |
12 |
|
T32 |
359 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14959284 |
1 |
|
|
T23 |
38182 |
|
T24 |
2629 |
|
T25 |
1259 |
| auto[1] |
868321 |
1 |
|
|
T24 |
310 |
|
T32 |
20 |
|
T113 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9094388 |
1 |
|
|
T23 |
38182 |
|
T24 |
1376 |
|
T25 |
1259 |
| auto[1] |
6733217 |
1 |
|
|
T24 |
1563 |
|
T30 |
10 |
|
T32 |
434 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2924777 |
1 |
|
|
T24 |
533 |
|
T30 |
9 |
|
T32 |
209 |
| auto[1] |
auto[0] |
auto[1] |
432988 |
1 |
|
|
T24 |
135 |
|
T32 |
9 |
|
T113 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2940119 |
1 |
|
|
T24 |
720 |
|
T30 |
1 |
|
T32 |
205 |
| auto[1] |
auto[1] |
auto[1] |
435333 |
1 |
|
|
T24 |
175 |
|
T32 |
11 |
|
T114 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9055387 |
1 |
|
|
T23 |
38182 |
|
T24 |
1291 |
|
T25 |
1259 |
| auto[1] |
6772218 |
1 |
|
|
T24 |
1648 |
|
T32 |
475 |
|
T113 |
213 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14960894 |
1 |
|
|
T23 |
38182 |
|
T24 |
2693 |
|
T25 |
1259 |
| auto[1] |
866711 |
1 |
|
|
T24 |
246 |
|
T32 |
16 |
|
T113 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9107918 |
1 |
|
|
T23 |
38182 |
|
T24 |
1652 |
|
T25 |
1259 |
| auto[1] |
6719687 |
1 |
|
|
T24 |
1287 |
|
T30 |
23 |
|
T32 |
434 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2927792 |
1 |
|
|
T24 |
455 |
|
T30 |
23 |
|
T32 |
171 |
| auto[1] |
auto[0] |
auto[1] |
432494 |
1 |
|
|
T24 |
104 |
|
T32 |
11 |
|
T113 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2925184 |
1 |
|
|
T24 |
586 |
|
T32 |
247 |
|
T113 |
108 |
| auto[1] |
auto[1] |
auto[1] |
434217 |
1 |
|
|
T24 |
142 |
|
T32 |
5 |
|
T113 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9108750 |
1 |
|
|
T23 |
38182 |
|
T24 |
1436 |
|
T25 |
1259 |
| auto[1] |
6718855 |
1 |
|
|
T24 |
1503 |
|
T32 |
480 |
|
T113 |
208 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14960312 |
1 |
|
|
T23 |
38182 |
|
T24 |
2603 |
|
T25 |
1259 |
| auto[1] |
867293 |
1 |
|
|
T24 |
336 |
|
T30 |
1 |
|
T32 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9092357 |
1 |
|
|
T23 |
38182 |
|
T24 |
1259 |
|
T25 |
1259 |
| auto[1] |
6735248 |
1 |
|
|
T24 |
1680 |
|
T30 |
23 |
|
T32 |
424 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2932910 |
1 |
|
|
T24 |
705 |
|
T30 |
22 |
|
T32 |
173 |
| auto[1] |
auto[0] |
auto[1] |
433056 |
1 |
|
|
T24 |
175 |
|
T30 |
1 |
|
T32 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2935045 |
1 |
|
|
T24 |
639 |
|
T32 |
239 |
|
T113 |
77 |
| auto[1] |
auto[1] |
auto[1] |
434237 |
1 |
|
|
T24 |
161 |
|
T32 |
4 |
|
T113 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9061822 |
1 |
|
|
T23 |
38182 |
|
T24 |
1448 |
|
T25 |
1259 |
| auto[1] |
6765783 |
1 |
|
|
T24 |
1491 |
|
T32 |
393 |
|
T113 |
206 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14957384 |
1 |
|
|
T23 |
38182 |
|
T24 |
2634 |
|
T25 |
1259 |
| auto[1] |
870221 |
1 |
|
|
T24 |
305 |
|
T30 |
1 |
|
T32 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9081371 |
1 |
|
|
T23 |
38182 |
|
T24 |
1415 |
|
T25 |
1259 |
| auto[1] |
6746234 |
1 |
|
|
T24 |
1524 |
|
T30 |
18 |
|
T32 |
560 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2939769 |
1 |
|
|
T24 |
625 |
|
T30 |
17 |
|
T32 |
292 |
| auto[1] |
auto[0] |
auto[1] |
434898 |
1 |
|
|
T24 |
156 |
|
T30 |
1 |
|
T32 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2936244 |
1 |
|
|
T24 |
594 |
|
T32 |
241 |
|
T113 |
95 |
| auto[1] |
auto[1] |
auto[1] |
435323 |
1 |
|
|
T24 |
149 |
|
T32 |
12 |
|
T113 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9074397 |
1 |
|
|
T23 |
38182 |
|
T24 |
1736 |
|
T25 |
1259 |
| auto[1] |
6753208 |
1 |
|
|
T24 |
1203 |
|
T30 |
14 |
|
T32 |
368 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14957442 |
1 |
|
|
T23 |
38182 |
|
T24 |
2625 |
|
T25 |
1259 |
| auto[1] |
870163 |
1 |
|
|
T24 |
314 |
|
T30 |
3 |
|
T32 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9077770 |
1 |
|
|
T23 |
38182 |
|
T24 |
1342 |
|
T25 |
1259 |
| auto[1] |
6749835 |
1 |
|
|
T24 |
1597 |
|
T30 |
18 |
|
T32 |
395 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2940150 |
1 |
|
|
T24 |
808 |
|
T30 |
10 |
|
T32 |
187 |
| auto[1] |
auto[0] |
auto[1] |
434441 |
1 |
|
|
T24 |
193 |
|
T30 |
1 |
|
T32 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2939522 |
1 |
|
|
T24 |
475 |
|
T30 |
5 |
|
T32 |
185 |
| auto[1] |
auto[1] |
auto[1] |
435722 |
1 |
|
|
T24 |
121 |
|
T30 |
2 |
|
T32 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9066356 |
1 |
|
|
T23 |
38182 |
|
T24 |
1736 |
|
T25 |
1259 |
| auto[1] |
6761249 |
1 |
|
|
T24 |
1203 |
|
T30 |
5 |
|
T32 |
442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14965307 |
1 |
|
|
T23 |
38182 |
|
T24 |
2674 |
|
T25 |
1259 |
| auto[1] |
862298 |
1 |
|
|
T24 |
265 |
|
T30 |
1 |
|
T32 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9121011 |
1 |
|
|
T23 |
38182 |
|
T24 |
1611 |
|
T25 |
1259 |
| auto[1] |
6706594 |
1 |
|
|
T24 |
1328 |
|
T30 |
10 |
|
T32 |
240 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2924738 |
1 |
|
|
T24 |
677 |
|
T30 |
9 |
|
T32 |
143 |
| auto[1] |
auto[0] |
auto[1] |
432043 |
1 |
|
|
T24 |
175 |
|
T30 |
1 |
|
T32 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2919558 |
1 |
|
|
T24 |
386 |
|
T32 |
88 |
|
T113 |
133 |
| auto[1] |
auto[1] |
auto[1] |
430255 |
1 |
|
|
T24 |
90 |
|
T32 |
1 |
|
T113 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9077850 |
1 |
|
|
T23 |
38182 |
|
T24 |
1359 |
|
T25 |
1259 |
| auto[1] |
6749755 |
1 |
|
|
T24 |
1580 |
|
T32 |
350 |
|
T113 |
239 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14961452 |
1 |
|
|
T23 |
38182 |
|
T24 |
2609 |
|
T25 |
1259 |
| auto[1] |
866153 |
1 |
|
|
T24 |
330 |
|
T30 |
1 |
|
T32 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9115220 |
1 |
|
|
T23 |
38182 |
|
T24 |
1197 |
|
T25 |
1259 |
| auto[1] |
6712385 |
1 |
|
|
T24 |
1742 |
|
T30 |
12 |
|
T32 |
481 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2900040 |
1 |
|
|
T24 |
616 |
|
T30 |
11 |
|
T32 |
231 |
| auto[1] |
auto[0] |
auto[1] |
429327 |
1 |
|
|
T24 |
147 |
|
T30 |
1 |
|
T32 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2946192 |
1 |
|
|
T24 |
796 |
|
T32 |
225 |
|
T113 |
77 |
| auto[1] |
auto[1] |
auto[1] |
436826 |
1 |
|
|
T24 |
183 |
|
T32 |
12 |
|
T113 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9095813 |
1 |
|
|
T23 |
38182 |
|
T24 |
1218 |
|
T25 |
1259 |
| auto[1] |
6731792 |
1 |
|
|
T24 |
1721 |
|
T30 |
9 |
|
T32 |
289 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14962528 |
1 |
|
|
T23 |
38182 |
|
T24 |
2626 |
|
T25 |
1259 |
| auto[1] |
865077 |
1 |
|
|
T24 |
313 |
|
T30 |
3 |
|
T32 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9114652 |
1 |
|
|
T23 |
38182 |
|
T24 |
1296 |
|
T25 |
1259 |
| auto[1] |
6712953 |
1 |
|
|
T24 |
1643 |
|
T30 |
25 |
|
T32 |
346 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2931863 |
1 |
|
|
T24 |
586 |
|
T30 |
14 |
|
T32 |
201 |
| auto[1] |
auto[0] |
auto[1] |
433788 |
1 |
|
|
T24 |
136 |
|
T30 |
2 |
|
T32 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2916013 |
1 |
|
|
T24 |
744 |
|
T30 |
8 |
|
T32 |
132 |
| auto[1] |
auto[1] |
auto[1] |
431289 |
1 |
|
|
T24 |
177 |
|
T30 |
1 |
|
T32 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9099276 |
1 |
|
|
T23 |
38182 |
|
T24 |
1317 |
|
T25 |
1259 |
| auto[1] |
6728329 |
1 |
|
|
T24 |
1622 |
|
T30 |
16 |
|
T32 |
458 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14957835 |
1 |
|
|
T23 |
38182 |
|
T24 |
2636 |
|
T25 |
1259 |
| auto[1] |
869770 |
1 |
|
|
T24 |
303 |
|
T30 |
2 |
|
T32 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9082730 |
1 |
|
|
T23 |
38182 |
|
T24 |
1437 |
|
T25 |
1259 |
| auto[1] |
6744875 |
1 |
|
|
T24 |
1502 |
|
T30 |
18 |
|
T32 |
489 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2947958 |
1 |
|
|
T24 |
540 |
|
T30 |
4 |
|
T32 |
207 |
| auto[1] |
auto[0] |
auto[1] |
436714 |
1 |
|
|
T24 |
137 |
|
T32 |
15 |
|
T113 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2927147 |
1 |
|
|
T24 |
659 |
|
T30 |
12 |
|
T32 |
255 |
| auto[1] |
auto[1] |
auto[1] |
433056 |
1 |
|
|
T24 |
166 |
|
T30 |
2 |
|
T32 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9109588 |
1 |
|
|
T23 |
38182 |
|
T24 |
1456 |
|
T25 |
1259 |
| auto[1] |
6718017 |
1 |
|
|
T24 |
1483 |
|
T30 |
5 |
|
T32 |
435 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14964250 |
1 |
|
|
T23 |
38182 |
|
T24 |
2667 |
|
T25 |
1259 |
| auto[1] |
863355 |
1 |
|
|
T24 |
272 |
|
T30 |
1 |
|
T32 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9117079 |
1 |
|
|
T23 |
38182 |
|
T24 |
1485 |
|
T25 |
1259 |
| auto[1] |
6710526 |
1 |
|
|
T24 |
1454 |
|
T30 |
18 |
|
T32 |
391 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2939769 |
1 |
|
|
T24 |
619 |
|
T30 |
17 |
|
T32 |
161 |
| auto[1] |
auto[0] |
auto[1] |
434074 |
1 |
|
|
T24 |
145 |
|
T30 |
1 |
|
T32 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2907402 |
1 |
|
|
T24 |
563 |
|
T32 |
211 |
|
T113 |
138 |
| auto[1] |
auto[1] |
auto[1] |
429281 |
1 |
|
|
T24 |
127 |
|
T32 |
11 |
|
T113 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9072813 |
1 |
|
|
T23 |
38182 |
|
T24 |
1521 |
|
T25 |
1259 |
| auto[1] |
6754792 |
1 |
|
|
T24 |
1418 |
|
T30 |
7 |
|
T32 |
496 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14963481 |
1 |
|
|
T23 |
38182 |
|
T24 |
2638 |
|
T25 |
1259 |
| auto[1] |
864124 |
1 |
|
|
T24 |
301 |
|
T32 |
20 |
|
T113 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9113495 |
1 |
|
|
T23 |
38182 |
|
T24 |
1448 |
|
T25 |
1259 |
| auto[1] |
6714110 |
1 |
|
|
T24 |
1491 |
|
T30 |
18 |
|
T32 |
505 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2909049 |
1 |
|
|
T24 |
608 |
|
T30 |
12 |
|
T32 |
188 |
| auto[1] |
auto[0] |
auto[1] |
428859 |
1 |
|
|
T24 |
154 |
|
T32 |
4 |
|
T113 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2940937 |
1 |
|
|
T24 |
582 |
|
T30 |
6 |
|
T32 |
297 |
| auto[1] |
auto[1] |
auto[1] |
435265 |
1 |
|
|
T24 |
147 |
|
T32 |
16 |
|
T113 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9112186 |
1 |
|
|
T23 |
38182 |
|
T24 |
1362 |
|
T25 |
1259 |
| auto[1] |
6715419 |
1 |
|
|
T24 |
1577 |
|
T30 |
5 |
|
T32 |
329 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14961398 |
1 |
|
|
T23 |
38182 |
|
T24 |
2574 |
|
T25 |
1259 |
| auto[1] |
866207 |
1 |
|
|
T24 |
365 |
|
T32 |
16 |
|
T113 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9110150 |
1 |
|
|
T23 |
38182 |
|
T24 |
1074 |
|
T25 |
1259 |
| auto[1] |
6717455 |
1 |
|
|
T24 |
1865 |
|
T30 |
5 |
|
T32 |
383 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2929985 |
1 |
|
|
T24 |
699 |
|
T30 |
5 |
|
T32 |
229 |
| auto[1] |
auto[0] |
auto[1] |
433510 |
1 |
|
|
T24 |
164 |
|
T32 |
11 |
|
T113 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2921263 |
1 |
|
|
T24 |
801 |
|
T32 |
138 |
|
T113 |
96 |
| auto[1] |
auto[1] |
auto[1] |
432697 |
1 |
|
|
T24 |
201 |
|
T32 |
5 |
|
T113 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9085842 |
1 |
|
|
T23 |
38182 |
|
T24 |
1379 |
|
T25 |
1259 |
| auto[1] |
6741763 |
1 |
|
|
T24 |
1560 |
|
T32 |
467 |
|
T113 |
224 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14959518 |
1 |
|
|
T23 |
38182 |
|
T24 |
2658 |
|
T25 |
1259 |
| auto[1] |
868087 |
1 |
|
|
T24 |
281 |
|
T30 |
3 |
|
T32 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9086785 |
1 |
|
|
T23 |
38182 |
|
T24 |
1513 |
|
T25 |
1259 |
| auto[1] |
6740820 |
1 |
|
|
T24 |
1426 |
|
T30 |
25 |
|
T32 |
600 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2938985 |
1 |
|
|
T24 |
577 |
|
T30 |
22 |
|
T32 |
273 |
| auto[1] |
auto[0] |
auto[1] |
434287 |
1 |
|
|
T24 |
149 |
|
T30 |
3 |
|
T32 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2933748 |
1 |
|
|
T24 |
568 |
|
T32 |
301 |
|
T113 |
93 |
| auto[1] |
auto[1] |
auto[1] |
433800 |
1 |
|
|
T24 |
132 |
|
T32 |
15 |
|
T113 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9084984 |
1 |
|
|
T23 |
38182 |
|
T24 |
1422 |
|
T25 |
1259 |
| auto[1] |
6742621 |
1 |
|
|
T24 |
1517 |
|
T30 |
16 |
|
T32 |
381 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14959537 |
1 |
|
|
T23 |
38182 |
|
T24 |
2589 |
|
T25 |
1259 |
| auto[1] |
868068 |
1 |
|
|
T24 |
350 |
|
T32 |
17 |
|
T113 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9101227 |
1 |
|
|
T23 |
38182 |
|
T24 |
1192 |
|
T25 |
1259 |
| auto[1] |
6726378 |
1 |
|
|
T24 |
1747 |
|
T30 |
18 |
|
T32 |
341 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2917294 |
1 |
|
|
T24 |
617 |
|
T30 |
5 |
|
T32 |
186 |
| auto[1] |
auto[0] |
auto[1] |
431845 |
1 |
|
|
T24 |
167 |
|
T32 |
12 |
|
T113 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2941016 |
1 |
|
|
T24 |
780 |
|
T30 |
13 |
|
T32 |
138 |
| auto[1] |
auto[1] |
auto[1] |
436223 |
1 |
|
|
T24 |
183 |
|
T32 |
5 |
|
T113 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9058801 |
1 |
|
|
T23 |
38182 |
|
T24 |
1705 |
|
T25 |
1259 |
| auto[1] |
6768804 |
1 |
|
|
T24 |
1234 |
|
T30 |
5 |
|
T32 |
395 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14957702 |
1 |
|
|
T23 |
38182 |
|
T24 |
2634 |
|
T25 |
1259 |
| auto[1] |
869903 |
1 |
|
|
T24 |
305 |
|
T30 |
1 |
|
T32 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9085718 |
1 |
|
|
T23 |
38182 |
|
T24 |
1371 |
|
T25 |
1259 |
| auto[1] |
6741887 |
1 |
|
|
T24 |
1568 |
|
T30 |
13 |
|
T32 |
429 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2919712 |
1 |
|
|
T24 |
675 |
|
T30 |
12 |
|
T32 |
207 |
| auto[1] |
auto[0] |
auto[1] |
432230 |
1 |
|
|
T24 |
159 |
|
T30 |
1 |
|
T32 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2952272 |
1 |
|
|
T24 |
588 |
|
T32 |
205 |
|
T113 |
85 |
| auto[1] |
auto[1] |
auto[1] |
437673 |
1 |
|
|
T24 |
146 |
|
T32 |
9 |
|
T113 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9119223 |
1 |
|
|
T23 |
38182 |
|
T24 |
1249 |
|
T25 |
1259 |
| auto[1] |
6708382 |
1 |
|
|
T24 |
1690 |
|
T30 |
5 |
|
T32 |
395 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14962836 |
1 |
|
|
T23 |
38182 |
|
T24 |
2663 |
|
T25 |
1259 |
| auto[1] |
864769 |
1 |
|
|
T24 |
276 |
|
T32 |
25 |
|
T113 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9102780 |
1 |
|
|
T23 |
38182 |
|
T24 |
1552 |
|
T25 |
1259 |
| auto[1] |
6724825 |
1 |
|
|
T24 |
1387 |
|
T30 |
5 |
|
T32 |
488 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2945112 |
1 |
|
|
T24 |
570 |
|
T30 |
5 |
|
T32 |
263 |
| auto[1] |
auto[0] |
auto[1] |
435818 |
1 |
|
|
T24 |
136 |
|
T32 |
13 |
|
T113 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2914944 |
1 |
|
|
T24 |
541 |
|
T32 |
200 |
|
T113 |
141 |
| auto[1] |
auto[1] |
auto[1] |
428951 |
1 |
|
|
T24 |
140 |
|
T32 |
12 |
|
T113 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9119113 |
1 |
|
|
T23 |
38182 |
|
T24 |
1517 |
|
T25 |
1259 |
| auto[1] |
6708492 |
1 |
|
|
T24 |
1422 |
|
T30 |
9 |
|
T32 |
408 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14964340 |
1 |
|
|
T23 |
38182 |
|
T24 |
2739 |
|
T25 |
1259 |
| auto[1] |
863265 |
1 |
|
|
T24 |
200 |
|
T30 |
1 |
|
T32 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9119687 |
1 |
|
|
T23 |
38182 |
|
T24 |
1933 |
|
T25 |
1259 |
| auto[1] |
6707918 |
1 |
|
|
T24 |
1006 |
|
T30 |
18 |
|
T32 |
323 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2928243 |
1 |
|
|
T24 |
401 |
|
T30 |
11 |
|
T32 |
208 |
| auto[1] |
auto[0] |
auto[1] |
433362 |
1 |
|
|
T24 |
106 |
|
T32 |
11 |
|
T113 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2916410 |
1 |
|
|
T24 |
405 |
|
T30 |
6 |
|
T32 |
98 |
| auto[1] |
auto[1] |
auto[1] |
429903 |
1 |
|
|
T24 |
94 |
|
T30 |
1 |
|
T32 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9117928 |
1 |
|
|
T23 |
38182 |
|
T24 |
1748 |
|
T25 |
1259 |
| auto[1] |
6709677 |
1 |
|
|
T24 |
1191 |
|
T30 |
14 |
|
T32 |
456 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14963426 |
1 |
|
|
T23 |
38182 |
|
T24 |
2670 |
|
T25 |
1259 |
| auto[1] |
864179 |
1 |
|
|
T24 |
269 |
|
T30 |
2 |
|
T32 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9123215 |
1 |
|
|
T23 |
38182 |
|
T24 |
1578 |
|
T25 |
1259 |
| auto[1] |
6704390 |
1 |
|
|
T24 |
1361 |
|
T30 |
25 |
|
T32 |
419 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2931483 |
1 |
|
|
T24 |
699 |
|
T30 |
16 |
|
T32 |
178 |
| auto[1] |
auto[0] |
auto[1] |
435173 |
1 |
|
|
T24 |
180 |
|
T32 |
8 |
|
T113 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2908728 |
1 |
|
|
T24 |
393 |
|
T30 |
7 |
|
T32 |
224 |
| auto[1] |
auto[1] |
auto[1] |
429006 |
1 |
|
|
T24 |
89 |
|
T30 |
2 |
|
T32 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9079281 |
1 |
|
|
T23 |
38182 |
|
T24 |
1255 |
|
T25 |
1259 |
| auto[1] |
6748324 |
1 |
|
|
T24 |
1684 |
|
T30 |
9 |
|
T32 |
399 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14956970 |
1 |
|
|
T23 |
38182 |
|
T24 |
2637 |
|
T25 |
1259 |
| auto[1] |
870635 |
1 |
|
|
T24 |
302 |
|
T32 |
13 |
|
T113 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9081181 |
1 |
|
|
T23 |
38182 |
|
T24 |
1409 |
|
T25 |
1259 |
| auto[1] |
6746424 |
1 |
|
|
T24 |
1530 |
|
T30 |
7 |
|
T32 |
415 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2943955 |
1 |
|
|
T24 |
514 |
|
T30 |
5 |
|
T32 |
250 |
| auto[1] |
auto[0] |
auto[1] |
437262 |
1 |
|
|
T24 |
123 |
|
T32 |
10 |
|
T113 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2931834 |
1 |
|
|
T24 |
714 |
|
T30 |
2 |
|
T32 |
152 |
| auto[1] |
auto[1] |
auto[1] |
433373 |
1 |
|
|
T24 |
179 |
|
T32 |
3 |
|
T113 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9077096 |
1 |
|
|
T23 |
38182 |
|
T24 |
1606 |
|
T25 |
1259 |
| auto[1] |
6750509 |
1 |
|
|
T24 |
1333 |
|
T30 |
14 |
|
T32 |
467 |