Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9095955 |
1 |
|
|
T23 |
38182 |
|
T24 |
1791 |
|
T25 |
1259 |
| auto[1] |
6731650 |
1 |
|
|
T24 |
1148 |
|
T32 |
407 |
|
T113 |
124 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14963015 |
1 |
|
|
T23 |
38182 |
|
T24 |
2592 |
|
T25 |
1259 |
| auto[1] |
864590 |
1 |
|
|
T24 |
347 |
|
T32 |
19 |
|
T113 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9112854 |
1 |
|
|
T23 |
38182 |
|
T24 |
1104 |
|
T25 |
1259 |
| auto[1] |
6714751 |
1 |
|
|
T24 |
1835 |
|
T32 |
451 |
|
T113 |
196 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2911111 |
1 |
|
|
T24 |
847 |
|
T32 |
182 |
|
T113 |
105 |
| auto[1] |
auto[0] |
auto[1] |
429337 |
1 |
|
|
T24 |
194 |
|
T32 |
8 |
|
T113 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2939050 |
1 |
|
|
T24 |
641 |
|
T32 |
250 |
|
T113 |
82 |
| auto[1] |
auto[1] |
auto[1] |
435253 |
1 |
|
|
T24 |
153 |
|
T32 |
11 |
|
T113 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |