Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9095399 |
1 |
|
|
T23 |
38182 |
|
T24 |
1356 |
|
T25 |
1259 |
| auto[1] |
6732206 |
1 |
|
|
T24 |
1583 |
|
T30 |
5 |
|
T32 |
438 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14955227 |
1 |
|
|
T23 |
38182 |
|
T24 |
2627 |
|
T25 |
1259 |
| auto[1] |
872378 |
1 |
|
|
T24 |
312 |
|
T32 |
13 |
|
T113 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9061668 |
1 |
|
|
T23 |
38182 |
|
T24 |
1397 |
|
T25 |
1259 |
| auto[1] |
6765937 |
1 |
|
|
T24 |
1542 |
|
T30 |
5 |
|
T32 |
349 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2950193 |
1 |
|
|
T24 |
555 |
|
T30 |
5 |
|
T32 |
116 |
| auto[1] |
auto[0] |
auto[1] |
437520 |
1 |
|
|
T24 |
133 |
|
T32 |
4 |
|
T113 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2943366 |
1 |
|
|
T24 |
675 |
|
T32 |
220 |
|
T113 |
75 |
| auto[1] |
auto[1] |
auto[1] |
434858 |
1 |
|
|
T24 |
179 |
|
T32 |
9 |
|
T113 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |