Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9092367 |
1 |
|
|
T23 |
38182 |
|
T24 |
1534 |
|
T25 |
1259 |
| auto[1] |
6735238 |
1 |
|
|
T24 |
1405 |
|
T30 |
21 |
|
T32 |
348 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14959708 |
1 |
|
|
T23 |
38182 |
|
T24 |
2704 |
|
T25 |
1259 |
| auto[1] |
867897 |
1 |
|
|
T24 |
235 |
|
T32 |
17 |
|
T113 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9089360 |
1 |
|
|
T23 |
38182 |
|
T24 |
1711 |
|
T25 |
1259 |
| auto[1] |
6738245 |
1 |
|
|
T24 |
1228 |
|
T30 |
18 |
|
T32 |
372 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2945050 |
1 |
|
|
T24 |
409 |
|
T30 |
4 |
|
T32 |
218 |
| auto[1] |
auto[0] |
auto[1] |
435610 |
1 |
|
|
T24 |
103 |
|
T32 |
9 |
|
T113 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2925298 |
1 |
|
|
T24 |
584 |
|
T30 |
14 |
|
T32 |
137 |
| auto[1] |
auto[1] |
auto[1] |
432287 |
1 |
|
|
T24 |
132 |
|
T32 |
8 |
|
T113 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |