Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9095005 |
1 |
|
|
T23 |
38182 |
|
T24 |
1316 |
|
T25 |
1259 |
auto[1] |
6732600 |
1 |
|
|
T24 |
1623 |
|
T30 |
14 |
|
T32 |
413 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14957999 |
1 |
|
|
T23 |
38182 |
|
T24 |
2655 |
|
T25 |
1259 |
auto[1] |
869606 |
1 |
|
|
T24 |
284 |
|
T30 |
1 |
|
T32 |
15 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9091076 |
1 |
|
|
T23 |
38182 |
|
T24 |
1453 |
|
T25 |
1259 |
auto[1] |
6736529 |
1 |
|
|
T24 |
1486 |
|
T30 |
23 |
|
T32 |
392 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2923822 |
1 |
|
|
T24 |
596 |
|
T30 |
16 |
|
T32 |
188 |
auto[1] |
auto[0] |
auto[1] |
432625 |
1 |
|
|
T24 |
139 |
|
T32 |
8 |
|
T113 |
3 |
auto[1] |
auto[1] |
auto[0] |
2943101 |
1 |
|
|
T24 |
606 |
|
T30 |
6 |
|
T32 |
189 |
auto[1] |
auto[1] |
auto[1] |
436981 |
1 |
|
|
T24 |
145 |
|
T30 |
1 |
|
T32 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |