Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9092911 |
1 |
|
|
T23 |
38182 |
|
T24 |
1330 |
|
T25 |
1259 |
| auto[1] |
6734694 |
1 |
|
|
T24 |
1609 |
|
T30 |
16 |
|
T32 |
383 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14961190 |
1 |
|
|
T23 |
38182 |
|
T24 |
2646 |
|
T25 |
1259 |
| auto[1] |
866415 |
1 |
|
|
T24 |
293 |
|
T30 |
1 |
|
T32 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9097322 |
1 |
|
|
T23 |
38182 |
|
T24 |
1328 |
|
T25 |
1259 |
| auto[1] |
6730283 |
1 |
|
|
T24 |
1611 |
|
T30 |
15 |
|
T32 |
274 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2939050 |
1 |
|
|
T24 |
542 |
|
T32 |
126 |
|
T113 |
90 |
| auto[1] |
auto[0] |
auto[1] |
435023 |
1 |
|
|
T24 |
118 |
|
T32 |
5 |
|
T113 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2924818 |
1 |
|
|
T24 |
776 |
|
T30 |
14 |
|
T32 |
140 |
| auto[1] |
auto[1] |
auto[1] |
431392 |
1 |
|
|
T24 |
175 |
|
T30 |
1 |
|
T32 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |