Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9055387 |
1 |
|
|
T23 |
38182 |
|
T24 |
1291 |
|
T25 |
1259 |
| auto[1] |
6772218 |
1 |
|
|
T24 |
1648 |
|
T32 |
475 |
|
T113 |
213 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13079688 |
1 |
|
|
T23 |
38182 |
|
T24 |
2151 |
|
T25 |
1259 |
| auto[1] |
2747917 |
1 |
|
|
T24 |
788 |
|
T30 |
1 |
|
T32 |
68 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9094830 |
1 |
|
|
T23 |
38182 |
|
T24 |
1444 |
|
T25 |
1259 |
| auto[1] |
6732775 |
1 |
|
|
T24 |
1495 |
|
T30 |
11 |
|
T32 |
408 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1992255 |
1 |
|
|
T24 |
314 |
|
T30 |
10 |
|
T32 |
115 |
| auto[1] |
auto[0] |
auto[1] |
1373406 |
1 |
|
|
T24 |
349 |
|
T30 |
1 |
|
T32 |
46 |
| auto[1] |
auto[1] |
auto[0] |
1992603 |
1 |
|
|
T24 |
393 |
|
T32 |
225 |
|
T113 |
80 |
| auto[1] |
auto[1] |
auto[1] |
1374511 |
1 |
|
|
T24 |
439 |
|
T32 |
22 |
|
T113 |
61 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |