Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9108750 |
1 |
|
|
T23 |
38182 |
|
T24 |
1436 |
|
T25 |
1259 |
| auto[1] |
6718855 |
1 |
|
|
T24 |
1503 |
|
T32 |
480 |
|
T113 |
208 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13069676 |
1 |
|
|
T23 |
38182 |
|
T24 |
2167 |
|
T25 |
1259 |
| auto[1] |
2757929 |
1 |
|
|
T24 |
772 |
|
T30 |
4 |
|
T32 |
88 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9073397 |
1 |
|
|
T23 |
38182 |
|
T24 |
1441 |
|
T25 |
1259 |
| auto[1] |
6754208 |
1 |
|
|
T24 |
1498 |
|
T30 |
7 |
|
T32 |
453 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2014799 |
1 |
|
|
T24 |
326 |
|
T30 |
3 |
|
T32 |
113 |
| auto[1] |
auto[0] |
auto[1] |
1386893 |
1 |
|
|
T24 |
361 |
|
T30 |
4 |
|
T32 |
38 |
| auto[1] |
auto[1] |
auto[0] |
1981480 |
1 |
|
|
T24 |
400 |
|
T32 |
252 |
|
T113 |
41 |
| auto[1] |
auto[1] |
auto[1] |
1371036 |
1 |
|
|
T24 |
411 |
|
T32 |
50 |
|
T113 |
35 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |