Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9061822 |
1 |
|
|
T23 |
38182 |
|
T24 |
1448 |
|
T25 |
1259 |
| auto[1] |
6765783 |
1 |
|
|
T24 |
1491 |
|
T32 |
393 |
|
T113 |
206 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13075035 |
1 |
|
|
T23 |
38182 |
|
T24 |
2233 |
|
T25 |
1259 |
| auto[1] |
2752570 |
1 |
|
|
T24 |
706 |
|
T32 |
50 |
|
T113 |
94 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9084287 |
1 |
|
|
T23 |
38182 |
|
T24 |
1479 |
|
T25 |
1259 |
| auto[1] |
6743318 |
1 |
|
|
T24 |
1460 |
|
T30 |
5 |
|
T32 |
399 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2005807 |
1 |
|
|
T24 |
361 |
|
T30 |
5 |
|
T32 |
199 |
| auto[1] |
auto[0] |
auto[1] |
1375127 |
1 |
|
|
T24 |
372 |
|
T32 |
36 |
|
T113 |
36 |
| auto[1] |
auto[1] |
auto[0] |
1984941 |
1 |
|
|
T24 |
393 |
|
T32 |
150 |
|
T113 |
70 |
| auto[1] |
auto[1] |
auto[1] |
1377443 |
1 |
|
|
T24 |
334 |
|
T32 |
14 |
|
T113 |
58 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |