Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9074397 |
1 |
|
|
T23 |
38182 |
|
T24 |
1736 |
|
T25 |
1259 |
| auto[1] |
6753208 |
1 |
|
|
T24 |
1203 |
|
T30 |
14 |
|
T32 |
368 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13081631 |
1 |
|
|
T23 |
38182 |
|
T24 |
1931 |
|
T25 |
1259 |
| auto[1] |
2745974 |
1 |
|
|
T24 |
1008 |
|
T30 |
8 |
|
T32 |
79 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9105726 |
1 |
|
|
T23 |
38182 |
|
T24 |
1031 |
|
T25 |
1259 |
| auto[1] |
6721879 |
1 |
|
|
T24 |
1908 |
|
T30 |
12 |
|
T32 |
372 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1981212 |
1 |
|
|
T24 |
474 |
|
T30 |
1 |
|
T32 |
181 |
| auto[1] |
auto[0] |
auto[1] |
1370147 |
1 |
|
|
T24 |
551 |
|
T30 |
6 |
|
T32 |
50 |
| auto[1] |
auto[1] |
auto[0] |
1994693 |
1 |
|
|
T24 |
426 |
|
T30 |
3 |
|
T32 |
112 |
| auto[1] |
auto[1] |
auto[1] |
1375827 |
1 |
|
|
T24 |
457 |
|
T30 |
2 |
|
T32 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |