Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14962419 |
1 |
|
|
T23 |
38182 |
|
T24 |
2667 |
|
T25 |
1259 |
| auto[1] |
865186 |
1 |
|
|
T24 |
272 |
|
T30 |
1 |
|
T32 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9094248 |
1 |
|
|
T23 |
38182 |
|
T24 |
1617 |
|
T25 |
1259 |
| auto[1] |
6733357 |
1 |
|
|
T24 |
1322 |
|
T30 |
20 |
|
T32 |
442 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2910227 |
1 |
|
|
T24 |
464 |
|
T30 |
11 |
|
T32 |
191 |
| auto[1] |
auto[0] |
auto[1] |
427085 |
1 |
|
|
T24 |
113 |
|
T32 |
8 |
|
T113 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2957944 |
1 |
|
|
T24 |
586 |
|
T30 |
8 |
|
T32 |
237 |
| auto[1] |
auto[1] |
auto[1] |
438101 |
1 |
|
|
T24 |
159 |
|
T30 |
1 |
|
T32 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |