Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9066356 |
1 |
|
|
T23 |
38182 |
|
T24 |
1736 |
|
T25 |
1259 |
| auto[1] |
6761249 |
1 |
|
|
T24 |
1203 |
|
T30 |
5 |
|
T32 |
442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13067524 |
1 |
|
|
T23 |
38182 |
|
T24 |
2275 |
|
T25 |
1259 |
| auto[1] |
2760081 |
1 |
|
|
T24 |
664 |
|
T30 |
14 |
|
T32 |
82 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9069153 |
1 |
|
|
T23 |
38182 |
|
T24 |
1645 |
|
T25 |
1259 |
| auto[1] |
6758452 |
1 |
|
|
T24 |
1294 |
|
T30 |
23 |
|
T32 |
363 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2002364 |
1 |
|
|
T24 |
347 |
|
T30 |
9 |
|
T32 |
165 |
| auto[1] |
auto[0] |
auto[1] |
1381197 |
1 |
|
|
T24 |
356 |
|
T30 |
10 |
|
T32 |
31 |
| auto[1] |
auto[1] |
auto[0] |
1996007 |
1 |
|
|
T24 |
283 |
|
T32 |
116 |
|
T113 |
65 |
| auto[1] |
auto[1] |
auto[1] |
1378884 |
1 |
|
|
T24 |
308 |
|
T30 |
4 |
|
T32 |
51 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |