Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9077850 |
1 |
|
|
T23 |
38182 |
|
T24 |
1359 |
|
T25 |
1259 |
| auto[1] |
6749755 |
1 |
|
|
T24 |
1580 |
|
T32 |
350 |
|
T113 |
239 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13077121 |
1 |
|
|
T23 |
38182 |
|
T24 |
2132 |
|
T25 |
1259 |
| auto[1] |
2750484 |
1 |
|
|
T24 |
807 |
|
T32 |
82 |
|
T113 |
67 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9088114 |
1 |
|
|
T23 |
38182 |
|
T24 |
1278 |
|
T25 |
1259 |
| auto[1] |
6739491 |
1 |
|
|
T24 |
1661 |
|
T30 |
3 |
|
T32 |
380 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1988501 |
1 |
|
|
T24 |
370 |
|
T30 |
3 |
|
T32 |
199 |
| auto[1] |
auto[0] |
auto[1] |
1371351 |
1 |
|
|
T24 |
343 |
|
T32 |
32 |
|
T113 |
31 |
| auto[1] |
auto[1] |
auto[0] |
2000506 |
1 |
|
|
T24 |
484 |
|
T32 |
99 |
|
T113 |
44 |
| auto[1] |
auto[1] |
auto[1] |
1379133 |
1 |
|
|
T24 |
464 |
|
T32 |
50 |
|
T113 |
36 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |