Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9095813 |
1 |
|
|
T23 |
38182 |
|
T24 |
1218 |
|
T25 |
1259 |
| auto[1] |
6731792 |
1 |
|
|
T24 |
1721 |
|
T30 |
9 |
|
T32 |
289 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13072346 |
1 |
|
|
T23 |
38182 |
|
T24 |
2275 |
|
T25 |
1259 |
| auto[1] |
2755259 |
1 |
|
|
T24 |
664 |
|
T30 |
11 |
|
T32 |
126 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9071319 |
1 |
|
|
T23 |
38182 |
|
T24 |
1597 |
|
T25 |
1259 |
| auto[1] |
6756286 |
1 |
|
|
T24 |
1342 |
|
T30 |
20 |
|
T32 |
465 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2006581 |
1 |
|
|
T24 |
250 |
|
T30 |
5 |
|
T32 |
222 |
| auto[1] |
auto[0] |
auto[1] |
1383030 |
1 |
|
|
T24 |
274 |
|
T30 |
6 |
|
T32 |
84 |
| auto[1] |
auto[1] |
auto[0] |
1994446 |
1 |
|
|
T24 |
428 |
|
T30 |
4 |
|
T32 |
117 |
| auto[1] |
auto[1] |
auto[1] |
1372229 |
1 |
|
|
T24 |
390 |
|
T30 |
5 |
|
T32 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |