Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9099276 |
1 |
|
|
T23 |
38182 |
|
T24 |
1317 |
|
T25 |
1259 |
| auto[1] |
6728329 |
1 |
|
|
T24 |
1622 |
|
T30 |
16 |
|
T32 |
458 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13090519 |
1 |
|
|
T23 |
38182 |
|
T24 |
2064 |
|
T25 |
1259 |
| auto[1] |
2737086 |
1 |
|
|
T24 |
875 |
|
T30 |
10 |
|
T32 |
91 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9133552 |
1 |
|
|
T23 |
38182 |
|
T24 |
1169 |
|
T25 |
1259 |
| auto[1] |
6694053 |
1 |
|
|
T24 |
1770 |
|
T30 |
12 |
|
T32 |
326 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1981904 |
1 |
|
|
T24 |
370 |
|
T30 |
2 |
|
T32 |
110 |
| auto[1] |
auto[0] |
auto[1] |
1371292 |
1 |
|
|
T24 |
389 |
|
T30 |
5 |
|
T32 |
42 |
| auto[1] |
auto[1] |
auto[0] |
1975063 |
1 |
|
|
T24 |
525 |
|
T32 |
125 |
|
T113 |
61 |
| auto[1] |
auto[1] |
auto[1] |
1365794 |
1 |
|
|
T24 |
486 |
|
T30 |
5 |
|
T32 |
49 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |