Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9109588 |
1 |
|
|
T23 |
38182 |
|
T24 |
1456 |
|
T25 |
1259 |
| auto[1] |
6718017 |
1 |
|
|
T24 |
1483 |
|
T30 |
5 |
|
T32 |
435 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13082339 |
1 |
|
|
T23 |
38182 |
|
T24 |
2010 |
|
T25 |
1259 |
| auto[1] |
2745266 |
1 |
|
|
T24 |
929 |
|
T30 |
3 |
|
T32 |
51 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9113945 |
1 |
|
|
T23 |
38182 |
|
T24 |
1183 |
|
T25 |
1259 |
| auto[1] |
6713660 |
1 |
|
|
T24 |
1756 |
|
T30 |
3 |
|
T32 |
349 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1998672 |
1 |
|
|
T24 |
472 |
|
T32 |
131 |
|
T113 |
20 |
| auto[1] |
auto[0] |
auto[1] |
1380095 |
1 |
|
|
T24 |
514 |
|
T30 |
3 |
|
T32 |
29 |
| auto[1] |
auto[1] |
auto[0] |
1969722 |
1 |
|
|
T24 |
355 |
|
T32 |
167 |
|
T113 |
33 |
| auto[1] |
auto[1] |
auto[1] |
1365171 |
1 |
|
|
T24 |
415 |
|
T32 |
22 |
|
T113 |
40 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |