Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9072813 |
1 |
|
|
T23 |
38182 |
|
T24 |
1521 |
|
T25 |
1259 |
| auto[1] |
6754792 |
1 |
|
|
T24 |
1418 |
|
T30 |
7 |
|
T32 |
496 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13081302 |
1 |
|
|
T23 |
38182 |
|
T24 |
2113 |
|
T25 |
1259 |
| auto[1] |
2746303 |
1 |
|
|
T24 |
826 |
|
T30 |
4 |
|
T32 |
112 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9100297 |
1 |
|
|
T23 |
38182 |
|
T24 |
1316 |
|
T25 |
1259 |
| auto[1] |
6727308 |
1 |
|
|
T24 |
1623 |
|
T30 |
12 |
|
T32 |
408 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1988136 |
1 |
|
|
T24 |
435 |
|
T30 |
4 |
|
T32 |
135 |
| auto[1] |
auto[0] |
auto[1] |
1370433 |
1 |
|
|
T24 |
430 |
|
T30 |
4 |
|
T32 |
24 |
| auto[1] |
auto[1] |
auto[0] |
1992869 |
1 |
|
|
T24 |
362 |
|
T30 |
4 |
|
T32 |
161 |
| auto[1] |
auto[1] |
auto[1] |
1375870 |
1 |
|
|
T24 |
396 |
|
T32 |
88 |
|
T113 |
40 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |