Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9112186 |
1 |
|
|
T23 |
38182 |
|
T24 |
1362 |
|
T25 |
1259 |
| auto[1] |
6715419 |
1 |
|
|
T24 |
1577 |
|
T30 |
5 |
|
T32 |
329 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13076227 |
1 |
|
|
T23 |
38182 |
|
T24 |
2224 |
|
T25 |
1259 |
| auto[1] |
2751378 |
1 |
|
|
T24 |
715 |
|
T30 |
9 |
|
T32 |
90 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9097870 |
1 |
|
|
T23 |
38182 |
|
T24 |
1537 |
|
T25 |
1259 |
| auto[1] |
6729735 |
1 |
|
|
T24 |
1402 |
|
T30 |
9 |
|
T32 |
382 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1996975 |
1 |
|
|
T24 |
341 |
|
T32 |
158 |
|
T113 |
39 |
| auto[1] |
auto[0] |
auto[1] |
1373638 |
1 |
|
|
T24 |
327 |
|
T30 |
5 |
|
T32 |
48 |
| auto[1] |
auto[1] |
auto[0] |
1981382 |
1 |
|
|
T24 |
346 |
|
T32 |
134 |
|
T113 |
48 |
| auto[1] |
auto[1] |
auto[1] |
1377740 |
1 |
|
|
T24 |
388 |
|
T30 |
4 |
|
T32 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |