Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9085842 |
1 |
|
|
T23 |
38182 |
|
T24 |
1379 |
|
T25 |
1259 |
| auto[1] |
6741763 |
1 |
|
|
T24 |
1560 |
|
T32 |
467 |
|
T113 |
224 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13088888 |
1 |
|
|
T23 |
38182 |
|
T24 |
2119 |
|
T25 |
1259 |
| auto[1] |
2738717 |
1 |
|
|
T24 |
820 |
|
T30 |
9 |
|
T32 |
108 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9124205 |
1 |
|
|
T23 |
38182 |
|
T24 |
1267 |
|
T25 |
1259 |
| auto[1] |
6703400 |
1 |
|
|
T24 |
1672 |
|
T30 |
20 |
|
T32 |
426 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1989196 |
1 |
|
|
T24 |
396 |
|
T30 |
11 |
|
T32 |
129 |
| auto[1] |
auto[0] |
auto[1] |
1374082 |
1 |
|
|
T24 |
392 |
|
T30 |
9 |
|
T32 |
37 |
| auto[1] |
auto[1] |
auto[0] |
1975487 |
1 |
|
|
T24 |
456 |
|
T32 |
189 |
|
T113 |
45 |
| auto[1] |
auto[1] |
auto[1] |
1364635 |
1 |
|
|
T24 |
428 |
|
T32 |
71 |
|
T113 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |