Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9084984 |
1 |
|
|
T23 |
38182 |
|
T24 |
1422 |
|
T25 |
1259 |
| auto[1] |
6742621 |
1 |
|
|
T24 |
1517 |
|
T30 |
16 |
|
T32 |
381 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13073248 |
1 |
|
|
T23 |
38182 |
|
T24 |
2165 |
|
T25 |
1259 |
| auto[1] |
2754357 |
1 |
|
|
T24 |
774 |
|
T30 |
22 |
|
T32 |
76 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9096009 |
1 |
|
|
T23 |
38182 |
|
T24 |
1369 |
|
T25 |
1259 |
| auto[1] |
6731596 |
1 |
|
|
T24 |
1570 |
|
T30 |
23 |
|
T32 |
348 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1998067 |
1 |
|
|
T24 |
396 |
|
T30 |
1 |
|
T32 |
152 |
| auto[1] |
auto[0] |
auto[1] |
1381183 |
1 |
|
|
T24 |
338 |
|
T30 |
9 |
|
T32 |
34 |
| auto[1] |
auto[1] |
auto[0] |
1979172 |
1 |
|
|
T24 |
400 |
|
T32 |
120 |
|
T113 |
80 |
| auto[1] |
auto[1] |
auto[1] |
1373174 |
1 |
|
|
T24 |
436 |
|
T30 |
13 |
|
T32 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |