Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9077744 |
1 |
|
|
T23 |
38182 |
|
T24 |
1414 |
|
T25 |
1259 |
| auto[1] |
6749861 |
1 |
|
|
T24 |
1525 |
|
T30 |
7 |
|
T32 |
425 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14962734 |
1 |
|
|
T23 |
38182 |
|
T24 |
2663 |
|
T25 |
1259 |
| auto[1] |
864871 |
1 |
|
|
T24 |
276 |
|
T32 |
21 |
|
T113 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9117845 |
1 |
|
|
T23 |
38182 |
|
T24 |
1442 |
|
T25 |
1259 |
| auto[1] |
6709760 |
1 |
|
|
T24 |
1497 |
|
T30 |
5 |
|
T32 |
380 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2923517 |
1 |
|
|
T24 |
653 |
|
T30 |
4 |
|
T32 |
162 |
| auto[1] |
auto[0] |
auto[1] |
432454 |
1 |
|
|
T24 |
148 |
|
T32 |
10 |
|
T114 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2921372 |
1 |
|
|
T24 |
568 |
|
T30 |
1 |
|
T32 |
197 |
| auto[1] |
auto[1] |
auto[1] |
432417 |
1 |
|
|
T24 |
128 |
|
T32 |
11 |
|
T113 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |