Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9119223 |
1 |
|
|
T23 |
38182 |
|
T24 |
1249 |
|
T25 |
1259 |
| auto[1] |
6708382 |
1 |
|
|
T24 |
1690 |
|
T30 |
5 |
|
T32 |
395 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13081425 |
1 |
|
|
T23 |
38182 |
|
T24 |
2109 |
|
T25 |
1259 |
| auto[1] |
2746180 |
1 |
|
|
T24 |
830 |
|
T30 |
9 |
|
T32 |
122 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9087045 |
1 |
|
|
T23 |
38182 |
|
T24 |
1310 |
|
T25 |
1259 |
| auto[1] |
6740560 |
1 |
|
|
T24 |
1629 |
|
T30 |
18 |
|
T32 |
411 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2020038 |
1 |
|
|
T24 |
325 |
|
T30 |
9 |
|
T32 |
147 |
| auto[1] |
auto[0] |
auto[1] |
1386527 |
1 |
|
|
T24 |
348 |
|
T30 |
5 |
|
T32 |
56 |
| auto[1] |
auto[1] |
auto[0] |
1974342 |
1 |
|
|
T24 |
474 |
|
T32 |
142 |
|
T113 |
42 |
| auto[1] |
auto[1] |
auto[1] |
1359653 |
1 |
|
|
T24 |
482 |
|
T30 |
4 |
|
T32 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |