Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9119113 |
1 |
|
|
T23 |
38182 |
|
T24 |
1517 |
|
T25 |
1259 |
| auto[1] |
6708492 |
1 |
|
|
T24 |
1422 |
|
T30 |
9 |
|
T32 |
408 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13085821 |
1 |
|
|
T23 |
38182 |
|
T24 |
2242 |
|
T25 |
1259 |
| auto[1] |
2741784 |
1 |
|
|
T24 |
697 |
|
T32 |
102 |
|
T113 |
84 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9111823 |
1 |
|
|
T23 |
38182 |
|
T24 |
1512 |
|
T25 |
1259 |
| auto[1] |
6715782 |
1 |
|
|
T24 |
1427 |
|
T30 |
4 |
|
T32 |
348 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1998319 |
1 |
|
|
T24 |
362 |
|
T30 |
4 |
|
T32 |
123 |
| auto[1] |
auto[0] |
auto[1] |
1383661 |
1 |
|
|
T24 |
367 |
|
T32 |
58 |
|
T113 |
27 |
| auto[1] |
auto[1] |
auto[0] |
1975679 |
1 |
|
|
T24 |
368 |
|
T32 |
123 |
|
T113 |
53 |
| auto[1] |
auto[1] |
auto[1] |
1358123 |
1 |
|
|
T24 |
330 |
|
T32 |
44 |
|
T113 |
57 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |