Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9117928 |
1 |
|
|
T23 |
38182 |
|
T24 |
1748 |
|
T25 |
1259 |
| auto[1] |
6709677 |
1 |
|
|
T24 |
1191 |
|
T30 |
14 |
|
T32 |
456 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13065263 |
1 |
|
|
T23 |
38182 |
|
T24 |
2098 |
|
T25 |
1259 |
| auto[1] |
2762342 |
1 |
|
|
T24 |
841 |
|
T30 |
3 |
|
T32 |
92 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9059985 |
1 |
|
|
T23 |
38182 |
|
T24 |
1342 |
|
T25 |
1259 |
| auto[1] |
6767620 |
1 |
|
|
T24 |
1597 |
|
T30 |
4 |
|
T32 |
520 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2010988 |
1 |
|
|
T24 |
464 |
|
T32 |
187 |
|
T113 |
47 |
| auto[1] |
auto[0] |
auto[1] |
1387332 |
1 |
|
|
T24 |
520 |
|
T32 |
42 |
|
T113 |
19 |
| auto[1] |
auto[1] |
auto[0] |
1994290 |
1 |
|
|
T24 |
292 |
|
T30 |
1 |
|
T32 |
241 |
| auto[1] |
auto[1] |
auto[1] |
1375010 |
1 |
|
|
T24 |
321 |
|
T30 |
3 |
|
T32 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |