Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9088763 |
1 |
|
|
T23 |
38182 |
|
T24 |
1701 |
|
T25 |
1259 |
| auto[1] |
6738842 |
1 |
|
|
T24 |
1238 |
|
T30 |
9 |
|
T32 |
277 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14956600 |
1 |
|
|
T23 |
38182 |
|
T24 |
2667 |
|
T25 |
1259 |
| auto[1] |
871005 |
1 |
|
|
T24 |
272 |
|
T30 |
1 |
|
T32 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9081263 |
1 |
|
|
T23 |
38182 |
|
T24 |
1649 |
|
T25 |
1259 |
| auto[1] |
6746342 |
1 |
|
|
T24 |
1290 |
|
T30 |
5 |
|
T32 |
378 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2945459 |
1 |
|
|
T24 |
592 |
|
T30 |
4 |
|
T32 |
223 |
| auto[1] |
auto[0] |
auto[1] |
436451 |
1 |
|
|
T24 |
157 |
|
T30 |
1 |
|
T32 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2929878 |
1 |
|
|
T24 |
426 |
|
T32 |
136 |
|
T113 |
71 |
| auto[1] |
auto[1] |
auto[1] |
434554 |
1 |
|
|
T24 |
115 |
|
T32 |
5 |
|
T113 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |