Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9120627 |
1 |
|
|
T23 |
38182 |
|
T24 |
1753 |
|
T25 |
1259 |
| auto[1] |
6706978 |
1 |
|
|
T24 |
1186 |
|
T30 |
21 |
|
T32 |
422 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14961618 |
1 |
|
|
T23 |
38182 |
|
T24 |
2679 |
|
T25 |
1259 |
| auto[1] |
865987 |
1 |
|
|
T24 |
260 |
|
T30 |
2 |
|
T32 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9100317 |
1 |
|
|
T23 |
38182 |
|
T24 |
1601 |
|
T25 |
1259 |
| auto[1] |
6727288 |
1 |
|
|
T24 |
1338 |
|
T30 |
18 |
|
T32 |
406 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2939954 |
1 |
|
|
T24 |
598 |
|
T30 |
4 |
|
T32 |
163 |
| auto[1] |
auto[0] |
auto[1] |
435312 |
1 |
|
|
T24 |
145 |
|
T30 |
1 |
|
T32 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2921347 |
1 |
|
|
T24 |
480 |
|
T30 |
12 |
|
T32 |
229 |
| auto[1] |
auto[1] |
auto[1] |
430675 |
1 |
|
|
T24 |
115 |
|
T30 |
1 |
|
T32 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |