Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9100955 |
1 |
|
|
T23 |
38182 |
|
T24 |
1695 |
|
T25 |
1259 |
| auto[1] |
6726650 |
1 |
|
|
T24 |
1244 |
|
T32 |
483 |
|
T113 |
267 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14961002 |
1 |
|
|
T23 |
38182 |
|
T24 |
2659 |
|
T25 |
1259 |
| auto[1] |
866603 |
1 |
|
|
T24 |
280 |
|
T32 |
21 |
|
T113 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9098751 |
1 |
|
|
T23 |
38182 |
|
T24 |
1486 |
|
T25 |
1259 |
| auto[1] |
6728854 |
1 |
|
|
T24 |
1453 |
|
T30 |
5 |
|
T32 |
419 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2932054 |
1 |
|
|
T24 |
729 |
|
T30 |
5 |
|
T32 |
166 |
| auto[1] |
auto[0] |
auto[1] |
431587 |
1 |
|
|
T24 |
171 |
|
T32 |
11 |
|
T113 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2930197 |
1 |
|
|
T24 |
444 |
|
T32 |
232 |
|
T113 |
97 |
| auto[1] |
auto[1] |
auto[1] |
435016 |
1 |
|
|
T24 |
109 |
|
T32 |
10 |
|
T113 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |