Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9069420 |
1 |
|
|
T23 |
38182 |
|
T24 |
1584 |
|
T25 |
1259 |
| auto[1] |
6758185 |
1 |
|
|
T24 |
1355 |
|
T30 |
21 |
|
T32 |
256 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14961000 |
1 |
|
|
T23 |
38182 |
|
T24 |
2688 |
|
T25 |
1259 |
| auto[1] |
866605 |
1 |
|
|
T24 |
251 |
|
T30 |
1 |
|
T32 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9098304 |
1 |
|
|
T23 |
38182 |
|
T24 |
1704 |
|
T25 |
1259 |
| auto[1] |
6729301 |
1 |
|
|
T24 |
1235 |
|
T30 |
23 |
|
T32 |
484 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2928600 |
1 |
|
|
T24 |
520 |
|
T30 |
10 |
|
T32 |
319 |
| auto[1] |
auto[0] |
auto[1] |
433116 |
1 |
|
|
T24 |
130 |
|
T32 |
16 |
|
T113 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2934096 |
1 |
|
|
T24 |
464 |
|
T30 |
12 |
|
T32 |
143 |
| auto[1] |
auto[1] |
auto[1] |
433489 |
1 |
|
|
T24 |
121 |
|
T30 |
1 |
|
T32 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |