Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9092779 |
1 |
|
|
T23 |
38182 |
|
T24 |
1237 |
|
T25 |
1259 |
| auto[1] |
6734826 |
1 |
|
|
T24 |
1702 |
|
T30 |
21 |
|
T32 |
318 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14961460 |
1 |
|
|
T23 |
38182 |
|
T24 |
2643 |
|
T25 |
1259 |
| auto[1] |
866145 |
1 |
|
|
T24 |
296 |
|
T30 |
3 |
|
T32 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9092561 |
1 |
|
|
T23 |
38182 |
|
T24 |
1483 |
|
T25 |
1259 |
| auto[1] |
6735044 |
1 |
|
|
T24 |
1456 |
|
T30 |
23 |
|
T32 |
454 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2923434 |
1 |
|
|
T24 |
456 |
|
T30 |
9 |
|
T32 |
287 |
| auto[1] |
auto[0] |
auto[1] |
430242 |
1 |
|
|
T24 |
120 |
|
T30 |
1 |
|
T32 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2945465 |
1 |
|
|
T24 |
704 |
|
T30 |
11 |
|
T32 |
147 |
| auto[1] |
auto[1] |
auto[1] |
435903 |
1 |
|
|
T24 |
176 |
|
T30 |
2 |
|
T32 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |