Unified Coverage Report :: Group Instance : intr_event_lvllow

Group Instance : intr_event_lvllow_pin23

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin23

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin23

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin23

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin24

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin24

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin24

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin24

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin25

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin25

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin25

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin25

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin26

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin26

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin26

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin26

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin27

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin27

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin27

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin27

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin28

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin28

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin28

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin28

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin29

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin29

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin29

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin29

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin3

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin30

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin30

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin30

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin30

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin31

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin31

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin31

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin31

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin5

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin6

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin7

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin8

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin8

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin8

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin8

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Go back
Group Instances:
intr_event_lvllow_pin23
intr_event_lvllow_pin24
intr_event_lvllow_pin25
intr_event_lvllow_pin26
intr_event_lvllow_pin27
intr_event_lvllow_pin28
intr_event_lvllow_pin29
intr_event_lvllow_pin3
intr_event_lvllow_pin30
intr_event_lvllow_pin31
intr_event_lvllow_pin4
intr_event_lvllow_pin5
intr_event_lvllow_pin6
intr_event_lvllow_pin7
intr_event_lvllow_pin8

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9119113

T23

38182

T24

1517

T25

1259

auto[1]

6708492

T24

1422

T30

T32

408

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11830556

T23

38182

T24

2160

T25

1259

auto[1]

3997049

T24

779

T30

T32

283

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9075427

T23

38182

T24

1422

T25

1259

auto[1]

6752178

T24

1517

T30

T32

393

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1382467

T24

346

T30

T32

auto[1]

auto[0]

auto[1]

1991913

T24

355

T32

150

T113

auto[1]

auto[0]

1372662

T24

392

T30

T32

auto[1]

2005136

T24

424

T30

T32

133

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9117928

T23

38182

T24

1748

T25

1259

auto[1]

6709677

T24

1191

T30

T32

456

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11856237

T23

38182

T24

2141

T25

1259

auto[1]

3971368

T24

798

T30

T32

319

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9112958

T23

38182

T24

1280

T25

1259

auto[1]

6714647

T24

1659

T30

T32

430

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1375902

T24

504

T30

T32

auto[1]

auto[0]

auto[1]

1988824

T24

481

T30

T32

153

auto[1]

auto[0]

1367377

T24

357

T32

T113

auto[1]

1982544

T24

317

T32

166

T113

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9079281

T23

38182

T24

1255

T25

1259

auto[1]

6748324

T24

1684

T30

T32

399

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11832769

T23

38182

T24

2187

T25

1259

auto[1]

3994836

T24

752

T30

T32

343

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9082293

T23

38182

T24

1414

T25

1259

auto[1]

6745312

T24

1525

T30

T32

423

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1376034

T24

322

T30

T32

auto[1]

auto[0]

auto[1]

1986292

T24

366

T30

T32

194

auto[1]

auto[0]

1374442

T24

451

T32

T113

auto[1]

2008544

T24

386

T32

149

T113

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9077096

T23

38182

T24

1606

T25

1259

auto[1]

6750509

T24

1333

T30

T32

467

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11841264

T23

38182

T24

2052

T25

1259

auto[1]

3986341

T24

887

T30

T32

371

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9091470

T23

38182

T24

1179

T25

1259

auto[1]

6736135

T24

1760

T30

T32

411

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1376567

T24

508

T30

T32

auto[1]

auto[0]

auto[1]

1995222

T24

495

T30

T32

160

auto[1]

auto[0]

1373227

T24

365

T30

T32

auto[1]

1991119

T24

392

T30

T32

211

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9077744

T23

38182

T24

1414

T25

1259

auto[1]

6749861

T24

1525

T30

T32

425

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11834167

T23

38182

T24

2118

T25

1259

auto[1]

3993438

T24

821

T30

T32

272

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9071211

T23

38182

T24

1281

T25

1259

auto[1]

6756394

T24

1658

T30

T32

384

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1376083

T24

343

T30

T32

auto[1]

auto[0]

auto[1]

1985156

T24

335

T30

T32

120

auto[1]

auto[0]

1386873

T24

494

T32

T113

auto[1]

2008282

T24

486

T32

152

T113

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9088763

T23

38182

T24

1701

T25

1259

auto[1]

6738842

T24

1238

T30

T32

277

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11856058

T23

38182

T24

2215

T25

1259

auto[1]

3971547

T24

724

T30

T32

324

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9114821

T23

38182

T24

1488

T25

1259

auto[1]

6712784

T24

1451

T30

T32

447

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1368848

T24

365

T30

T32

auto[1]

auto[0]

auto[1]

1982114

T24

400

T30

T32

187

auto[1]

auto[0]

1372389

T24

362

T32

T113

auto[1]

1989433

T24

324

T30

T32

137

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9109087

T23

38182

T24

1409

T25

1259

auto[1]

6718518

T24

1530

T30

T32

359

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11854668

T23

38182

T24

2287

T25

1259

auto[1]

3972937

T24

652

T30

T32

322

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9109434

T23

38182

T24

1669

T25

1259

auto[1]

6718171

T24

1270

T30

T32

419

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1381448

T24

287

T30

T32

auto[1]

auto[0]

auto[1]

2001347

T24

309

T30

T32

160

auto[1]

auto[0]

1363786

T24

331

T30

T32

auto[1]

1971590

T24

343

T32

162

T113

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9120627

T23

38182

T24

1753

T25

1259

auto[1]

6706978

T24

1186

T30

T32

422

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11854605

T23

38182

T24

2283

T25

1259

auto[1]

3973000

T24

656

T32

255

T113

124

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9113553

T23

38182

T24

1578

T25

1259

auto[1]

6714052

T24

1361

T30

T32

310

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1377482

T24

400

T30

T32

auto[1]

auto[0]

auto[1]

1996075

T24

378

T32

100

T113

auto[1]

auto[0]

1363570

T24

305

T32

T113

auto[1]

1976925

T24

278

T32

155

T113

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9100955

T23

38182

T24

1695

T25

1259

auto[1]

6726650

T24

1244

T32

483

T113

267

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11848306

T23

38182

T24

2167

T25

1259

auto[1]

3979299

T24

772

T30

T32

379

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9092355

T23

38182

T24

1440

T25

1259

auto[1]

6735250

T24

1499

T30

T32

460

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1381469

T24

436

T30

T32

auto[1]

auto[0]

auto[1]

1995439

T24

502

T30

T32

159

auto[1]

auto[0]

1374482

T24

291

T32

T113

auto[1]

1983860

T24

270

T32

220

T113

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9069420

T23

38182

T24

1584

T25

1259

auto[1]

6758185

T24

1355

T30

T32

256

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11832748

T23

38182

T24

2276

T25

1259

auto[1]

3994857

T24

663

T30

T32

273

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9073498

T23

38182

T24

1542

T25

1259

auto[1]

6754107

T24

1397

T30

T32

337

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1374709

T24

382

T32

T113

auto[1]

auto[0]

auto[1]

1986006

T24

354

T30

T32

156

auto[1]

auto[0]

1384541

T24

352

T30

T32

auto[1]

2008851

T24

309

T30

T32

117

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9092779

T23

38182

T24

1237

T25

1259

auto[1]

6734826

T24

1702

T30

T32

318

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11835736

T23

38182

T24

2237

T25

1259

auto[1]

3991869

T24

702

T30

T32

315

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9078280

T23

38182

T24

1527

T25

1259

auto[1]

6749325

T24

1412

T30

T32

395

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1383361

T24

337

T30

T32

auto[1]

auto[0]

auto[1]

1996274

T24

352

T30

T32

157

auto[1]

auto[0]

1374095

T24

373

T30

T32

auto[1]

1995595

T24

350

T30

T32

158

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9095955

T23

38182

T24

1791

T25

1259

auto[1]

6731650

T24

1148

T32

407

T113

124

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11850836

T23

38182

T24

2240

T25

1259

auto[1]

3976769

T24

699

T30

T32

356

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9105212

T23

38182

T24

1481

T25

1259

auto[1]

6722393

T24

1458

T30

T32

440

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1374417

T24

421

T30

T32

auto[1]

auto[0]

auto[1]

1990733

T24

377

T30

T32

149

auto[1]

auto[0]

1371207

T24

338

T32

T113

auto[1]

1986036

T24

322

T32

207

T113

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9095399

T23

38182

T24

1356

T25

1259

auto[1]

6732206

T24

1583

T30

T32

438

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11861876

T23

38182

T24

2338

T25

1259

auto[1]

3965729

T24

601

T30

T32

241

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9117827

T23

38182

T24

1742

T25

1259

auto[1]

6709778

T24

1197

T30

T32

298

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1374037

T24

214

T30

T32

auto[1]

auto[0]

auto[1]

1978312

T24

216

T30

T32

120

auto[1]

auto[0]

1370012

T24

382

T32

T113

auto[1]

1987417

T24

385

T32

121

T113

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9092367

T23

38182

T24

1534

T25

1259

auto[1]

6735238

T24

1405

T30

T32

348

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11837347

T23

38182

T24

2116

T25

1259

auto[1]

3990258

T24

823

T30

T32

355

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9085080

T23

38182

T24

1244

T25

1259

auto[1]

6742525

T24

1695

T30

T32

437

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1372110

T24

502

T30

T32

auto[1]

auto[0]

auto[1]

1993066

T24

448

T30

T32

184

auto[1]

auto[0]

1380157

T24

370

T30

T32

auto[1]

1997192

T24

375

T30

T32

171

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9095005

T23

38182

T24

1316

T25

1259

auto[1]

6732600

T24

1623

T30

T32

413

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11868083

T23

38182

T24

2192

T25

1259

auto[1]

3959522

T24

747

T30

T32

294

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9132967

T23

38182

T24

1359

T25

1259

auto[1]

6694638

T24

1580

T30

T32

433

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

1367350

T24

358

T32

T113

auto[1]

auto[0]

auto[1]

1979527

T24

325

T30

T32

150

auto[1]

auto[0]

1367766

T24

475

T30

T32

auto[1]

1979995

T24

422

T30

T32

144

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded