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Group Instance : intr_event_rising_pin7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_rising_pin7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_rising_pin7
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_rising_pin7
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_rising_pin8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_rising_pin8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_rising_pin8
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_rising_pin8
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_rising_pin9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_rising_pin9

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_rising_pin9
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_rising_pin9
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0

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Group Instances:
intr_event_rising_pin7
intr_event_rising_pin8
intr_event_rising_pin9

Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9092367 1 T23 38182 T24 1534 T25 1259
auto[1] 6735238 1 T24 1405 T30 21 T32 348


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14959245 1 T23 38182 T24 2711 T25 1259
auto[1] 868360 1 T24 228 T30 1 T32 18


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9079362 1 T23 38182 T24 1771 T25 1259
auto[1] 6748243 1 T24 1168 T30 19 T32 480


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 2949522 1 T24 466 T30 3 T32 276
auto[1] auto[0] auto[1] 435620 1 T24 117 T32 11 T113 2
auto[1] auto[1] auto[0] 2930361 1 T24 474 T30 15 T32 186
auto[1] auto[1] auto[1] 432740 1 T24 111 T30 1 T32 7


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9095005 1 T23 38182 T24 1316 T25 1259
auto[1] 6732600 1 T24 1623 T30 14 T32 413


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14956997 1 T23 38182 T24 2684 T25 1259
auto[1] 870608 1 T24 255 T32 18 T113 14


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9087071 1 T23 38182 T24 1615 T25 1259
auto[1] 6740534 1 T24 1324 T32 325 T113 222


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 2928864 1 T24 361 T32 105 T113 109
auto[1] auto[0] auto[1] 433388 1 T24 81 T32 8 T113 7
auto[1] auto[1] auto[0] 2941062 1 T24 708 T32 202 T113 99
auto[1] auto[1] auto[1] 437220 1 T24 174 T32 10 T113 7


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9092911 1 T23 38182 T24 1330 T25 1259
auto[1] 6734694 1 T24 1609 T30 16 T32 383


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14961670 1 T23 38182 T24 2654 T25 1259
auto[1] 865935 1 T24 285 T30 1 T32 17


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9107523 1 T23 38182 T24 1456 T25 1259
auto[1] 6720082 1 T24 1483 T30 19 T32 479


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 2947957 1 T24 609 T30 3 T32 225
auto[1] auto[0] auto[1] 437163 1 T24 143 T32 8 T113 6
auto[1] auto[1] auto[0] 2906190 1 T24 589 T30 15 T32 237
auto[1] auto[1] auto[1] 428772 1 T24 142 T30 1 T32 9


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

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