Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 947
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T769 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2429117810 Apr 25 12:33:05 PM PDT 24 Apr 25 12:33:09 PM PDT 24 17979062 ps
T92 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.884432706 Apr 25 12:32:41 PM PDT 24 Apr 25 12:32:43 PM PDT 24 31880069 ps
T770 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.385381535 Apr 25 12:32:39 PM PDT 24 Apr 25 12:32:41 PM PDT 24 61945036 ps
T771 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3007028128 Apr 25 12:32:33 PM PDT 24 Apr 25 12:32:35 PM PDT 24 16546265 ps
T772 /workspace/coverage/cover_reg_top/35.gpio_intr_test.26136944 Apr 25 12:33:06 PM PDT 24 Apr 25 12:33:09 PM PDT 24 52544777 ps
T773 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1986305877 Apr 25 12:33:01 PM PDT 24 Apr 25 12:33:05 PM PDT 24 12954558 ps
T774 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1578414295 Apr 25 12:32:58 PM PDT 24 Apr 25 12:33:00 PM PDT 24 42039818 ps
T775 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2075314590 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:03 PM PDT 24 24417329 ps
T776 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1610091004 Apr 25 12:32:57 PM PDT 24 Apr 25 12:33:01 PM PDT 24 579377502 ps
T777 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.646757096 Apr 25 12:32:37 PM PDT 24 Apr 25 12:32:40 PM PDT 24 55835106 ps
T778 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.717484626 Apr 25 12:32:58 PM PDT 24 Apr 25 12:33:01 PM PDT 24 80684116 ps
T779 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2617659618 Apr 25 12:33:01 PM PDT 24 Apr 25 12:33:05 PM PDT 24 176410057 ps
T780 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1263477967 Apr 25 12:33:01 PM PDT 24 Apr 25 12:33:06 PM PDT 24 30606960 ps
T781 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2470463468 Apr 25 12:32:47 PM PDT 24 Apr 25 12:32:48 PM PDT 24 47429019 ps
T105 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2658497526 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:03 PM PDT 24 46596544 ps
T782 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3699557258 Apr 25 12:32:49 PM PDT 24 Apr 25 12:32:51 PM PDT 24 26424493 ps
T783 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2754476699 Apr 25 12:32:50 PM PDT 24 Apr 25 12:32:51 PM PDT 24 34040300 ps
T784 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1103401664 Apr 25 12:32:33 PM PDT 24 Apr 25 12:32:36 PM PDT 24 89023349 ps
T785 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1190519552 Apr 25 12:33:00 PM PDT 24 Apr 25 12:33:05 PM PDT 24 105570463 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2674891865 Apr 25 12:32:32 PM PDT 24 Apr 25 12:32:35 PM PDT 24 16256679 ps
T93 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2248632519 Apr 25 12:32:51 PM PDT 24 Apr 25 12:32:55 PM PDT 24 1052106662 ps
T787 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2060540278 Apr 25 12:32:48 PM PDT 24 Apr 25 12:32:50 PM PDT 24 27397431 ps
T788 /workspace/coverage/cover_reg_top/32.gpio_intr_test.562501800 Apr 25 12:33:03 PM PDT 24 Apr 25 12:33:07 PM PDT 24 41587052 ps
T789 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3072830487 Apr 25 12:33:06 PM PDT 24 Apr 25 12:33:09 PM PDT 24 112903223 ps
T790 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3329413624 Apr 25 12:32:48 PM PDT 24 Apr 25 12:32:50 PM PDT 24 112747197 ps
T106 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2644901730 Apr 25 12:32:40 PM PDT 24 Apr 25 12:32:42 PM PDT 24 26902642 ps
T791 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3560881161 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:04 PM PDT 24 131005821 ps
T792 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1036049359 Apr 25 12:32:49 PM PDT 24 Apr 25 12:32:51 PM PDT 24 41620206 ps
T793 /workspace/coverage/cover_reg_top/4.gpio_intr_test.30876239 Apr 25 12:32:39 PM PDT 24 Apr 25 12:32:42 PM PDT 24 12827744 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.781128827 Apr 25 12:32:33 PM PDT 24 Apr 25 12:32:36 PM PDT 24 46397199 ps
T53 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2929832391 Apr 25 12:33:00 PM PDT 24 Apr 25 12:33:04 PM PDT 24 71267174 ps
T95 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1441668799 Apr 25 12:33:03 PM PDT 24 Apr 25 12:33:08 PM PDT 24 12317163 ps
T107 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3449977203 Apr 25 12:32:51 PM PDT 24 Apr 25 12:32:53 PM PDT 24 33541645 ps
T794 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2780738867 Apr 25 12:32:40 PM PDT 24 Apr 25 12:32:43 PM PDT 24 160286575 ps
T795 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3132792360 Apr 25 12:32:52 PM PDT 24 Apr 25 12:32:54 PM PDT 24 26665643 ps
T796 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1605954974 Apr 25 12:33:03 PM PDT 24 Apr 25 12:33:07 PM PDT 24 12234617 ps
T797 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1257349584 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:04 PM PDT 24 71700887 ps
T96 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1805594993 Apr 25 12:32:52 PM PDT 24 Apr 25 12:32:54 PM PDT 24 20922764 ps
T798 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3949828917 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:02 PM PDT 24 117259434 ps
T799 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1879349312 Apr 25 12:32:39 PM PDT 24 Apr 25 12:32:42 PM PDT 24 17829853 ps
T800 /workspace/coverage/cover_reg_top/21.gpio_intr_test.1517198818 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:03 PM PDT 24 34483812 ps
T801 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1988476034 Apr 25 12:33:06 PM PDT 24 Apr 25 12:33:09 PM PDT 24 24253354 ps
T802 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1455251634 Apr 25 12:32:38 PM PDT 24 Apr 25 12:32:40 PM PDT 24 25033707 ps
T803 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4249132784 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:13 PM PDT 24 14132866 ps
T804 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.504227755 Apr 25 12:32:58 PM PDT 24 Apr 25 12:33:01 PM PDT 24 31774018 ps
T97 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3078376646 Apr 25 12:32:33 PM PDT 24 Apr 25 12:32:36 PM PDT 24 68472625 ps
T98 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2880674656 Apr 25 12:32:42 PM PDT 24 Apr 25 12:32:44 PM PDT 24 40655378 ps
T805 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3269167743 Apr 25 12:32:58 PM PDT 24 Apr 25 12:33:00 PM PDT 24 16766116 ps
T806 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2073384301 Apr 25 12:33:02 PM PDT 24 Apr 25 12:33:06 PM PDT 24 23672496 ps
T807 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.677894511 Apr 25 12:33:03 PM PDT 24 Apr 25 12:33:07 PM PDT 24 52214838 ps
T808 /workspace/coverage/cover_reg_top/28.gpio_intr_test.733293740 Apr 25 12:33:04 PM PDT 24 Apr 25 12:33:08 PM PDT 24 31442990 ps
T809 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2540916171 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:03 PM PDT 24 136800161 ps
T810 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1123327630 Apr 25 12:33:03 PM PDT 24 Apr 25 12:33:08 PM PDT 24 15738331 ps
T811 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3637308991 Apr 25 12:32:48 PM PDT 24 Apr 25 12:32:50 PM PDT 24 26017413 ps
T101 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.881153907 Apr 25 12:32:39 PM PDT 24 Apr 25 12:32:41 PM PDT 24 19975657 ps
T812 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1406522471 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:03 PM PDT 24 13962585 ps
T111 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1469292677 Apr 25 12:32:49 PM PDT 24 Apr 25 12:32:51 PM PDT 24 161611475 ps
T813 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.774427371 Apr 25 12:32:58 PM PDT 24 Apr 25 12:33:00 PM PDT 24 318371216 ps
T814 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3938600765 Apr 25 12:32:51 PM PDT 24 Apr 25 12:32:53 PM PDT 24 18273443 ps
T815 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2376359254 Apr 25 12:32:42 PM PDT 24 Apr 25 12:32:44 PM PDT 24 148470364 ps
T816 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2483922385 Apr 25 12:32:38 PM PDT 24 Apr 25 12:32:40 PM PDT 24 339654860 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2757133044 Apr 25 12:32:38 PM PDT 24 Apr 25 12:32:40 PM PDT 24 84609859 ps
T818 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4278533316 Apr 25 12:32:50 PM PDT 24 Apr 25 12:32:52 PM PDT 24 22828046 ps
T819 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2071994980 Apr 25 12:32:33 PM PDT 24 Apr 25 12:32:38 PM PDT 24 122722691 ps
T820 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3558533035 Apr 25 12:32:50 PM PDT 24 Apr 25 12:32:52 PM PDT 24 190690392 ps
T821 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1758869167 Apr 25 12:32:39 PM PDT 24 Apr 25 12:32:44 PM PDT 24 751266749 ps
T822 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1188910376 Apr 25 12:32:49 PM PDT 24 Apr 25 12:32:51 PM PDT 24 15792927 ps
T823 /workspace/coverage/cover_reg_top/5.gpio_intr_test.582758776 Apr 25 12:32:50 PM PDT 24 Apr 25 12:32:52 PM PDT 24 28276768 ps
T824 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.510119764 Apr 25 12:32:48 PM PDT 24 Apr 25 12:32:51 PM PDT 24 256559041 ps
T51 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.623720714 Apr 25 12:33:00 PM PDT 24 Apr 25 12:33:05 PM PDT 24 99826094 ps
T825 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2311278484 Apr 25 12:32:48 PM PDT 24 Apr 25 12:32:50 PM PDT 24 13053964 ps
T826 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.89533941 Apr 25 12:33:04 PM PDT 24 Apr 25 12:33:08 PM PDT 24 32714520 ps
T827 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2010413045 Apr 25 12:32:58 PM PDT 24 Apr 25 12:33:01 PM PDT 24 45898054 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2625156539 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:02 PM PDT 24 61036498 ps
T112 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3490302467 Apr 25 12:32:48 PM PDT 24 Apr 25 12:32:49 PM PDT 24 327532767 ps
T829 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1115626152 Apr 25 12:32:31 PM PDT 24 Apr 25 12:32:33 PM PDT 24 32050740 ps
T830 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.208670812 Apr 25 12:33:01 PM PDT 24 Apr 25 12:33:06 PM PDT 24 103313872 ps
T831 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.744038082 Apr 25 12:33:02 PM PDT 24 Apr 25 12:33:07 PM PDT 24 77114072 ps
T832 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.694181511 Apr 25 12:32:38 PM PDT 24 Apr 25 12:32:39 PM PDT 24 24513557 ps
T833 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3221068097 Apr 25 12:33:06 PM PDT 24 Apr 25 12:33:09 PM PDT 24 13926091 ps
T834 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1591919564 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:04 PM PDT 24 50174030 ps
T835 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.117216808 Apr 25 12:32:43 PM PDT 24 Apr 25 12:32:44 PM PDT 24 21659592 ps
T836 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.471664446 Apr 25 12:33:02 PM PDT 24 Apr 25 12:33:07 PM PDT 24 47332130 ps
T99 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.324935650 Apr 25 12:32:43 PM PDT 24 Apr 25 12:32:47 PM PDT 24 296226895 ps
T837 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2089756589 Apr 25 12:33:01 PM PDT 24 Apr 25 12:33:06 PM PDT 24 71301886 ps
T838 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.209226971 Apr 25 12:32:51 PM PDT 24 Apr 25 12:32:53 PM PDT 24 105354313 ps
T100 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.965403679 Apr 25 12:32:38 PM PDT 24 Apr 25 12:32:43 PM PDT 24 323613426 ps
T839 /workspace/coverage/cover_reg_top/27.gpio_intr_test.435402748 Apr 25 12:33:00 PM PDT 24 Apr 25 12:33:04 PM PDT 24 17677638 ps
T840 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1730989038 Apr 25 12:32:58 PM PDT 24 Apr 25 12:33:02 PM PDT 24 528267704 ps
T841 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3438003326 Apr 25 12:33:01 PM PDT 24 Apr 25 12:33:05 PM PDT 24 44663608 ps
T49 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3913171785 Apr 25 12:32:59 PM PDT 24 Apr 25 12:33:03 PM PDT 24 164661722 ps
T842 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3317465055 Apr 25 12:33:01 PM PDT 24 Apr 25 12:33:05 PM PDT 24 36766685 ps
T843 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2992362917 Apr 25 12:33:05 PM PDT 24 Apr 25 12:33:09 PM PDT 24 128242697 ps
T844 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.502890134 Apr 25 12:32:48 PM PDT 24 Apr 25 12:32:52 PM PDT 24 59496119 ps
T845 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2774737785 Apr 25 12:33:06 PM PDT 24 Apr 25 12:33:09 PM PDT 24 48261925 ps
T846 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4185230286 Apr 25 12:33:01 PM PDT 24 Apr 25 12:33:07 PM PDT 24 448286103 ps
T847 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1780256885 Apr 25 12:32:57 PM PDT 24 Apr 25 12:32:58 PM PDT 24 135710950 ps
T848 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054113135 Apr 25 12:33:29 PM PDT 24 Apr 25 12:33:34 PM PDT 24 163602579 ps
T849 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2933991726 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:28 PM PDT 24 82983453 ps
T850 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2803154481 Apr 25 12:32:33 PM PDT 24 Apr 25 12:32:37 PM PDT 24 186629611 ps
T851 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4242400645 Apr 25 12:32:06 PM PDT 24 Apr 25 12:32:08 PM PDT 24 137522120 ps
T852 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1701215888 Apr 25 12:32:13 PM PDT 24 Apr 25 12:32:15 PM PDT 24 221996638 ps
T853 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1141826745 Apr 25 12:32:23 PM PDT 24 Apr 25 12:32:24 PM PDT 24 161679417 ps
T854 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2722162072 Apr 25 12:33:41 PM PDT 24 Apr 25 12:33:44 PM PDT 24 241483410 ps
T855 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1082003488 Apr 25 12:32:27 PM PDT 24 Apr 25 12:32:30 PM PDT 24 346441482 ps
T856 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1375758145 Apr 25 12:32:19 PM PDT 24 Apr 25 12:32:21 PM PDT 24 320353601 ps
T857 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.694681697 Apr 25 12:32:17 PM PDT 24 Apr 25 12:32:19 PM PDT 24 1559084934 ps
T858 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2149316041 Apr 25 12:32:26 PM PDT 24 Apr 25 12:32:29 PM PDT 24 63744282 ps
T859 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3465937948 Apr 25 12:32:04 PM PDT 24 Apr 25 12:32:06 PM PDT 24 161752686 ps
T860 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1109311410 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:28 PM PDT 24 77265250 ps
T861 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.135999559 Apr 25 12:32:26 PM PDT 24 Apr 25 12:32:29 PM PDT 24 223852400 ps
T862 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3162220721 Apr 25 12:32:26 PM PDT 24 Apr 25 12:32:29 PM PDT 24 271055483 ps
T863 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2422463181 Apr 25 12:32:32 PM PDT 24 Apr 25 12:32:34 PM PDT 24 86584287 ps
T864 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3415692696 Apr 25 12:32:26 PM PDT 24 Apr 25 12:32:29 PM PDT 24 212305885 ps
T865 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3350788033 Apr 25 12:32:23 PM PDT 24 Apr 25 12:32:24 PM PDT 24 134776365 ps
T866 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2188905544 Apr 25 12:32:05 PM PDT 24 Apr 25 12:32:08 PM PDT 24 263899775 ps
T867 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2452740878 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:28 PM PDT 24 596027911 ps
T868 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2393418502 Apr 25 12:32:09 PM PDT 24 Apr 25 12:32:10 PM PDT 24 523448713 ps
T869 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1481507834 Apr 25 12:32:30 PM PDT 24 Apr 25 12:32:32 PM PDT 24 166376748 ps
T870 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2341514070 Apr 25 12:32:07 PM PDT 24 Apr 25 12:32:09 PM PDT 24 188233056 ps
T871 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2724671688 Apr 25 12:32:18 PM PDT 24 Apr 25 12:32:20 PM PDT 24 202559538 ps
T872 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2867867786 Apr 25 12:32:18 PM PDT 24 Apr 25 12:32:21 PM PDT 24 163390755 ps
T873 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1161880459 Apr 25 12:32:12 PM PDT 24 Apr 25 12:32:15 PM PDT 24 142729284 ps
T874 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4107060173 Apr 25 12:32:31 PM PDT 24 Apr 25 12:32:32 PM PDT 24 32882944 ps
T875 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513617751 Apr 25 12:32:13 PM PDT 24 Apr 25 12:32:16 PM PDT 24 207440423 ps
T876 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.959440476 Apr 25 12:32:19 PM PDT 24 Apr 25 12:32:21 PM PDT 24 150106093 ps
T877 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1327501841 Apr 25 12:32:10 PM PDT 24 Apr 25 12:32:13 PM PDT 24 285558471 ps
T878 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1393269657 Apr 25 12:32:13 PM PDT 24 Apr 25 12:32:16 PM PDT 24 343901084 ps
T879 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1936741353 Apr 25 12:32:20 PM PDT 24 Apr 25 12:32:22 PM PDT 24 52282201 ps
T880 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1425474173 Apr 25 12:32:18 PM PDT 24 Apr 25 12:32:21 PM PDT 24 236432903 ps
T881 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.294389249 Apr 25 12:32:20 PM PDT 24 Apr 25 12:32:22 PM PDT 24 107449419 ps
T882 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.541094584 Apr 25 12:32:17 PM PDT 24 Apr 25 12:32:18 PM PDT 24 73036023 ps
T883 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1608331629 Apr 25 12:32:19 PM PDT 24 Apr 25 12:32:21 PM PDT 24 94988948 ps
T884 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3509390615 Apr 25 12:32:24 PM PDT 24 Apr 25 12:32:26 PM PDT 24 61069659 ps
T885 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3773266959 Apr 25 12:32:19 PM PDT 24 Apr 25 12:32:21 PM PDT 24 224845832 ps
T886 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2452635837 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:27 PM PDT 24 51617698 ps
T887 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2973044025 Apr 25 12:32:14 PM PDT 24 Apr 25 12:32:17 PM PDT 24 174287878 ps
T888 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1022350218 Apr 25 12:32:10 PM PDT 24 Apr 25 12:32:13 PM PDT 24 84397127 ps
T889 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.271490406 Apr 25 12:32:04 PM PDT 24 Apr 25 12:32:06 PM PDT 24 205528520 ps
T890 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3685042543 Apr 25 12:32:13 PM PDT 24 Apr 25 12:32:16 PM PDT 24 56057337 ps
T891 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4058958880 Apr 25 12:32:32 PM PDT 24 Apr 25 12:32:35 PM PDT 24 661731457 ps
T892 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2476323991 Apr 25 12:32:19 PM PDT 24 Apr 25 12:32:21 PM PDT 24 135450472 ps
T893 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.476460447 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:27 PM PDT 24 125961756 ps
T894 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1259930404 Apr 25 12:32:33 PM PDT 24 Apr 25 12:32:37 PM PDT 24 185726724 ps
T895 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3181115910 Apr 25 12:32:12 PM PDT 24 Apr 25 12:32:16 PM PDT 24 187939208 ps
T896 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.122993445 Apr 25 12:32:04 PM PDT 24 Apr 25 12:32:06 PM PDT 24 146517243 ps
T897 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4232914226 Apr 25 12:32:13 PM PDT 24 Apr 25 12:32:16 PM PDT 24 38306733 ps
T898 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2124840333 Apr 25 12:32:24 PM PDT 24 Apr 25 12:32:27 PM PDT 24 250240165 ps
T899 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3653772933 Apr 25 12:32:33 PM PDT 24 Apr 25 12:32:35 PM PDT 24 100591129 ps
T900 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.682359029 Apr 25 12:32:17 PM PDT 24 Apr 25 12:32:19 PM PDT 24 186183663 ps
T901 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3205157014 Apr 25 12:32:05 PM PDT 24 Apr 25 12:32:07 PM PDT 24 116866681 ps
T902 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2093993432 Apr 25 12:32:11 PM PDT 24 Apr 25 12:32:13 PM PDT 24 174392616 ps
T903 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2102136335 Apr 25 12:32:33 PM PDT 24 Apr 25 12:32:36 PM PDT 24 179121272 ps
T904 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3465942203 Apr 25 12:32:32 PM PDT 24 Apr 25 12:32:35 PM PDT 24 111767535 ps
T905 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1179884890 Apr 25 12:32:16 PM PDT 24 Apr 25 12:32:18 PM PDT 24 30287848 ps
T906 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3324114560 Apr 25 12:32:11 PM PDT 24 Apr 25 12:32:14 PM PDT 24 60161463 ps
T907 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1028809015 Apr 25 12:32:13 PM PDT 24 Apr 25 12:32:16 PM PDT 24 124789467 ps
T908 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3070967793 Apr 25 12:33:29 PM PDT 24 Apr 25 12:33:34 PM PDT 24 622454327 ps
T909 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3272141246 Apr 25 12:32:12 PM PDT 24 Apr 25 12:32:14 PM PDT 24 100033196 ps
T910 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4013458503 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:28 PM PDT 24 153499106 ps
T911 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3366011123 Apr 25 12:32:30 PM PDT 24 Apr 25 12:32:32 PM PDT 24 92141500 ps
T912 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.650835593 Apr 25 12:32:18 PM PDT 24 Apr 25 12:32:20 PM PDT 24 166135648 ps
T913 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2538337881 Apr 25 12:33:41 PM PDT 24 Apr 25 12:33:44 PM PDT 24 274809382 ps
T914 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1286737395 Apr 25 12:32:11 PM PDT 24 Apr 25 12:32:13 PM PDT 24 60390070 ps
T915 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3903447400 Apr 25 12:33:41 PM PDT 24 Apr 25 12:33:44 PM PDT 24 69817995 ps
T916 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1214392679 Apr 25 12:32:13 PM PDT 24 Apr 25 12:32:16 PM PDT 24 130595852 ps
T917 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3148535780 Apr 25 12:32:31 PM PDT 24 Apr 25 12:32:33 PM PDT 24 173317470 ps
T918 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2758611626 Apr 25 12:32:12 PM PDT 24 Apr 25 12:32:16 PM PDT 24 1154389999 ps
T919 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3199185751 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:28 PM PDT 24 157821003 ps
T920 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1796257296 Apr 25 12:32:17 PM PDT 24 Apr 25 12:32:19 PM PDT 24 242021368 ps
T921 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.294784281 Apr 25 12:32:07 PM PDT 24 Apr 25 12:32:09 PM PDT 24 987715644 ps
T922 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1497842444 Apr 25 12:32:17 PM PDT 24 Apr 25 12:32:19 PM PDT 24 577396910 ps
T923 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3567304902 Apr 25 12:32:11 PM PDT 24 Apr 25 12:32:14 PM PDT 24 102284556 ps
T924 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1100523303 Apr 25 12:32:31 PM PDT 24 Apr 25 12:32:33 PM PDT 24 395310862 ps
T925 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1992594919 Apr 25 12:32:23 PM PDT 24 Apr 25 12:32:25 PM PDT 24 54698006 ps
T926 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3903566135 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:28 PM PDT 24 58611908 ps
T927 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.460572262 Apr 25 12:32:17 PM PDT 24 Apr 25 12:32:19 PM PDT 24 35137394 ps
T928 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3081092566 Apr 25 12:33:40 PM PDT 24 Apr 25 12:33:44 PM PDT 24 58006434 ps
T929 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4169731792 Apr 25 12:32:19 PM PDT 24 Apr 25 12:32:21 PM PDT 24 38944881 ps
T930 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1978160698 Apr 25 12:32:05 PM PDT 24 Apr 25 12:32:07 PM PDT 24 247274911 ps
T931 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.609721508 Apr 25 12:32:19 PM PDT 24 Apr 25 12:32:21 PM PDT 24 323934971 ps
T932 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.120678149 Apr 25 12:32:14 PM PDT 24 Apr 25 12:32:16 PM PDT 24 37433388 ps
T933 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1817380095 Apr 25 12:32:10 PM PDT 24 Apr 25 12:32:13 PM PDT 24 34925986 ps
T934 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3545409260 Apr 25 12:32:16 PM PDT 24 Apr 25 12:32:18 PM PDT 24 172874887 ps
T935 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3281779300 Apr 25 12:32:11 PM PDT 24 Apr 25 12:32:14 PM PDT 24 56993673 ps
T936 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4108171599 Apr 25 12:32:19 PM PDT 24 Apr 25 12:32:22 PM PDT 24 331298036 ps
T937 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3732507482 Apr 25 12:32:15 PM PDT 24 Apr 25 12:32:17 PM PDT 24 43765498 ps
T938 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.946050691 Apr 25 12:32:05 PM PDT 24 Apr 25 12:32:07 PM PDT 24 28528230 ps
T939 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3549804836 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:28 PM PDT 24 128780141 ps
T940 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4137768417 Apr 25 12:32:07 PM PDT 24 Apr 25 12:32:09 PM PDT 24 107004134 ps
T941 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3724618321 Apr 25 12:32:25 PM PDT 24 Apr 25 12:32:28 PM PDT 24 34223749 ps
T942 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.353025953 Apr 25 12:32:12 PM PDT 24 Apr 25 12:32:15 PM PDT 24 179374541 ps
T943 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.387837331 Apr 25 12:32:06 PM PDT 24 Apr 25 12:32:08 PM PDT 24 161860171 ps
T944 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3425460458 Apr 25 12:32:10 PM PDT 24 Apr 25 12:32:12 PM PDT 24 236984662 ps
T945 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2811431146 Apr 25 12:32:17 PM PDT 24 Apr 25 12:32:19 PM PDT 24 451385193 ps
T946 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1823199230 Apr 25 12:33:41 PM PDT 24 Apr 25 12:33:44 PM PDT 24 183028507 ps
T947 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2388303303 Apr 25 12:32:14 PM PDT 24 Apr 25 12:32:16 PM PDT 24 64905643 ps

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.72803957
Short name T32
Test name
Test status
Simulation time 57816676 ps
CPU time 2.66 seconds
Started Apr 25 12:43:06 PM PDT 24
Finished Apr 25 12:43:12 PM PDT 24
Peak memory 197968 kb
Host smart-9e711d11-3c1c-4882-adc9-0e36b1c2567f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72803957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand
om_long_reg_writes_reg_reads.72803957
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1752369241
Short name T116
Test name
Test status
Simulation time 158037494 ps
CPU time 3.29 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 198120 kb
Host smart-af20f4bc-9e47-45fd-8008-7bf3a417c73d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752369241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1752369241
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.700319094
Short name T12
Test name
Test status
Simulation time 55436240258 ps
CPU time 1365.56 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 01:06:41 PM PDT 24
Peak memory 198296 kb
Host smart-dd120d2a-20b1-492b-a69a-579e9c7ee64d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=700319094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.700319094
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4214488502
Short name T19
Test name
Test status
Simulation time 62037522 ps
CPU time 0.84 seconds
Started Apr 25 12:42:46 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 213936 kb
Host smart-81087104-cc89-4b7b-9e3d-5c5f23d663be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214488502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4214488502
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3522195227
Short name T81
Test name
Test status
Simulation time 238410131 ps
CPU time 1.52 seconds
Started Apr 25 12:32:30 PM PDT 24
Finished Apr 25 12:32:33 PM PDT 24
Peak memory 197112 kb
Host smart-b70eb2b5-9fdb-46ab-afb7-6da957ca4df7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522195227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3522195227
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.229287297
Short name T6
Test name
Test status
Simulation time 163456879 ps
CPU time 2.16 seconds
Started Apr 25 12:42:59 PM PDT 24
Finished Apr 25 12:43:04 PM PDT 24
Peak memory 197964 kb
Host smart-8c8a8b7e-5122-4189-b05b-2052c5df25db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229287297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.229287297
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_alert_test.866738441
Short name T46
Test name
Test status
Simulation time 14806651 ps
CPU time 0.61 seconds
Started Apr 25 12:43:44 PM PDT 24
Finished Apr 25 12:43:46 PM PDT 24
Peak memory 194868 kb
Host smart-3216d8dd-46e1-4939-99f4-0206e3cc1305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866738441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.866738441
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.4190071739
Short name T47
Test name
Test status
Simulation time 226074703 ps
CPU time 1.47 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:33:10 PM PDT 24
Peak memory 197448 kb
Host smart-1c4379a1-8440-41c4-8395-3e6b4b8488b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190071739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.4190071739
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.229591662
Short name T83
Test name
Test status
Simulation time 16338390 ps
CPU time 0.72 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:36 PM PDT 24
Peak memory 195204 kb
Host smart-f3ea2cea-b658-4bf1-bdeb-00be198ae01f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229591662 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.229591662
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.623720714
Short name T51
Test name
Test status
Simulation time 99826094 ps
CPU time 1.13 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:05 PM PDT 24
Peak memory 197536 kb
Host smart-10e6e498-519f-4bcc-81c2-9fcae8fc39a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623720714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.623720714
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.392647960
Short name T24
Test name
Test status
Simulation time 1599639491 ps
CPU time 3.05 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:33 PM PDT 24
Peak memory 197288 kb
Host smart-f820169f-48ef-46b4-98f2-917db9f63e6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392647960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
392647960
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.744038082
Short name T831
Test name
Test status
Simulation time 77114072 ps
CPU time 1.15 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 197604 kb
Host smart-bc6f0b4e-3eed-44cd-8dc1-85c6c857a156
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744038082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.744038082
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3007028128
Short name T771
Test name
Test status
Simulation time 16546265 ps
CPU time 0.69 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:35 PM PDT 24
Peak memory 193948 kb
Host smart-d3dd1ff7-1c14-4719-af77-7647ed5000ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007028128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3007028128
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3078376646
Short name T97
Test name
Test status
Simulation time 68472625 ps
CPU time 0.63 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:36 PM PDT 24
Peak memory 194232 kb
Host smart-769ebbb7-e076-4a3d-baf9-dc6138dfb189
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078376646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3078376646
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1103401664
Short name T784
Test name
Test status
Simulation time 89023349 ps
CPU time 1.17 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:36 PM PDT 24
Peak memory 197680 kb
Host smart-0840dc67-f01a-4f5b-b9e2-b1126c67e514
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103401664 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1103401664
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.458740795
Short name T767
Test name
Test status
Simulation time 18599009 ps
CPU time 0.61 seconds
Started Apr 25 12:32:32 PM PDT 24
Finished Apr 25 12:32:35 PM PDT 24
Peak memory 192840 kb
Host smart-28f47033-f644-4773-9478-1c16aab1228c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458740795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.458740795
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2674891865
Short name T786
Test name
Test status
Simulation time 16256679 ps
CPU time 0.7 seconds
Started Apr 25 12:32:32 PM PDT 24
Finished Apr 25 12:32:35 PM PDT 24
Peak memory 193200 kb
Host smart-c9130ac8-c340-4f99-a96e-dc5a60450176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674891865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2674891865
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1115626152
Short name T829
Test name
Test status
Simulation time 32050740 ps
CPU time 0.65 seconds
Started Apr 25 12:32:31 PM PDT 24
Finished Apr 25 12:32:33 PM PDT 24
Peak memory 194908 kb
Host smart-72f2d3a3-f9bb-499d-9639-32ef7351f7a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115626152 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1115626152
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2071994980
Short name T819
Test name
Test status
Simulation time 122722691 ps
CPU time 2.41 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:38 PM PDT 24
Peak memory 197540 kb
Host smart-333c39bf-af13-469d-a7e6-79c34d4b9d69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071994980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2071994980
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3010090626
Short name T761
Test name
Test status
Simulation time 51075636 ps
CPU time 0.87 seconds
Started Apr 25 12:32:32 PM PDT 24
Finished Apr 25 12:32:35 PM PDT 24
Peak memory 196680 kb
Host smart-292ebb1e-01b2-4982-a0b7-1ae022986a1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010090626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3010090626
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.781128827
Short name T94
Test name
Test status
Simulation time 46397199 ps
CPU time 0.79 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:36 PM PDT 24
Peak memory 195368 kb
Host smart-c7ead55d-282e-44c5-9277-6e71e59840cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781128827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.781128827
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.965403679
Short name T100
Test name
Test status
Simulation time 323613426 ps
CPU time 2.99 seconds
Started Apr 25 12:32:38 PM PDT 24
Finished Apr 25 12:32:43 PM PDT 24
Peak memory 197580 kb
Host smart-27c70c5d-2a77-40f3-9482-71f9ccce996e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965403679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.965403679
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.117216808
Short name T835
Test name
Test status
Simulation time 21659592 ps
CPU time 0.66 seconds
Started Apr 25 12:32:43 PM PDT 24
Finished Apr 25 12:32:44 PM PDT 24
Peak memory 194148 kb
Host smart-013cb1a5-37a6-478f-96cc-d7a7a7c93097
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117216808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.117216808
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2115750959
Short name T735
Test name
Test status
Simulation time 66805875 ps
CPU time 1.05 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:41 PM PDT 24
Peak memory 197444 kb
Host smart-a14c4886-d35b-4885-b23d-00c1158b059b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115750959 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2115750959
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.636543347
Short name T765
Test name
Test status
Simulation time 39505146 ps
CPU time 0.59 seconds
Started Apr 25 12:32:32 PM PDT 24
Finished Apr 25 12:32:34 PM PDT 24
Peak memory 194444 kb
Host smart-ad1cd178-9018-4192-b927-23b7906a8e97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636543347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.636543347
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2786116205
Short name T729
Test name
Test status
Simulation time 39542024 ps
CPU time 0.57 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:42 PM PDT 24
Peak memory 193856 kb
Host smart-38a81f3c-944c-45d3-b055-6730f569284f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786116205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2786116205
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.678908721
Short name T726
Test name
Test status
Simulation time 138849394 ps
CPU time 1.4 seconds
Started Apr 25 12:32:41 PM PDT 24
Finished Apr 25 12:32:44 PM PDT 24
Peak memory 197552 kb
Host smart-6ce2beec-c500-42ea-a746-6b4d8294c019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678908721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.678908721
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2780738867
Short name T794
Test name
Test status
Simulation time 160286575 ps
CPU time 0.86 seconds
Started Apr 25 12:32:40 PM PDT 24
Finished Apr 25 12:32:43 PM PDT 24
Peak memory 196412 kb
Host smart-28aec88b-d371-4f7e-872d-a90303ed1264
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780738867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2780738867
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.504227755
Short name T804
Test name
Test status
Simulation time 31774018 ps
CPU time 0.72 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:01 PM PDT 24
Peak memory 197404 kb
Host smart-1e17055b-67c0-47d3-8b87-00d5a3faf54e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504227755 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.504227755
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1578414295
Short name T774
Test name
Test status
Simulation time 42039818 ps
CPU time 0.57 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:00 PM PDT 24
Peak memory 192904 kb
Host smart-301e393f-ec63-41c2-abb4-4c6cd4ba9d7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578414295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1578414295
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1860852345
Short name T745
Test name
Test status
Simulation time 14763264 ps
CPU time 0.58 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 193180 kb
Host smart-1ae1627c-d9d9-40d4-a652-2cf2d8505f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860852345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1860852345
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1780256885
Short name T847
Test name
Test status
Simulation time 135710950 ps
CPU time 0.79 seconds
Started Apr 25 12:32:57 PM PDT 24
Finished Apr 25 12:32:58 PM PDT 24
Peak memory 196536 kb
Host smart-35e86fad-4669-4211-b503-c09cbe876c99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780256885 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1780256885
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1450334173
Short name T727
Test name
Test status
Simulation time 211885470 ps
CPU time 2.63 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 197480 kb
Host smart-79f5b683-f17f-483e-a0df-b11a14f1bda1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450334173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1450334173
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.652318502
Short name T743
Test name
Test status
Simulation time 26604505 ps
CPU time 0.83 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:05 PM PDT 24
Peak memory 197468 kb
Host smart-24624731-0f92-4c36-b661-266469e9f7f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652318502 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.652318502
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.4243643149
Short name T110
Test name
Test status
Simulation time 47859635 ps
CPU time 0.59 seconds
Started Apr 25 12:32:57 PM PDT 24
Finished Apr 25 12:32:59 PM PDT 24
Peak memory 194888 kb
Host smart-4ebf9436-059b-4c05-af74-a0f240bcad53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243643149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.4243643149
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1406522471
Short name T812
Test name
Test status
Simulation time 13962585 ps
CPU time 0.6 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 193812 kb
Host smart-c88b4f0f-9fc2-4030-bbe7-69ba54b267cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406522471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1406522471
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.971885443
Short name T104
Test name
Test status
Simulation time 20493096 ps
CPU time 0.67 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:00 PM PDT 24
Peak memory 194360 kb
Host smart-b268e017-ac5e-4d13-9ac8-fd72becbb110
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971885443 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.971885443
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3070148356
Short name T753
Test name
Test status
Simulation time 133280165 ps
CPU time 2.51 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 197544 kb
Host smart-1fcdc67b-1174-4ddf-91ec-354b20b6979a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070148356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3070148356
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3913171785
Short name T49
Test name
Test status
Simulation time 164661722 ps
CPU time 1.23 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 197612 kb
Host smart-6a7bb35d-b929-4b2c-b652-c28b65b7bc67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913171785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3913171785
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.208670812
Short name T830
Test name
Test status
Simulation time 103313872 ps
CPU time 0.89 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 197536 kb
Host smart-86bc887c-1e0e-463b-839a-fdefc651c794
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208670812 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.208670812
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.499290256
Short name T85
Test name
Test status
Simulation time 15053264 ps
CPU time 0.6 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 194524 kb
Host smart-ca357e7f-2a28-46e9-a31c-a9e89e54449b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499290256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.499290256
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.300188450
Short name T756
Test name
Test status
Simulation time 16549381 ps
CPU time 0.63 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:00 PM PDT 24
Peak memory 193224 kb
Host smart-21890940-2f05-43c0-a907-c3cee7446fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300188450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.300188450
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.774427371
Short name T813
Test name
Test status
Simulation time 318371216 ps
CPU time 0.77 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:00 PM PDT 24
Peak memory 195752 kb
Host smart-1c200c4b-0cec-4d2c-9e53-d9ecf341e71d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774427371 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.774427371
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1257349584
Short name T797
Test name
Test status
Simulation time 71700887 ps
CPU time 1.99 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 197580 kb
Host smart-2595d9b7-1059-4b51-992a-720e70d652f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257349584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1257349584
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.325789300
Short name T48
Test name
Test status
Simulation time 146522284 ps
CPU time 0.84 seconds
Started Apr 25 12:32:57 PM PDT 24
Finished Apr 25 12:32:58 PM PDT 24
Peak memory 196716 kb
Host smart-c0cda9cb-99ba-4682-a47e-99d583e009d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325789300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.325789300
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4185230286
Short name T846
Test name
Test status
Simulation time 448286103 ps
CPU time 1.86 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 197580 kb
Host smart-f9e3afaa-c6b2-4443-8f23-5956cbf6c422
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185230286 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4185230286
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3832192672
Short name T744
Test name
Test status
Simulation time 17924822 ps
CPU time 0.59 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 193780 kb
Host smart-a4cc4cd3-3c7b-4823-8446-d594cb1cc32e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832192672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3832192672
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2606939669
Short name T725
Test name
Test status
Simulation time 19101698 ps
CPU time 0.62 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:01 PM PDT 24
Peak memory 193312 kb
Host smart-544773bc-4a1c-4e2b-8064-62dcc1cc8c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606939669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2606939669
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.486460925
Short name T82
Test name
Test status
Simulation time 31845003 ps
CPU time 0.75 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 195704 kb
Host smart-cf0328f5-eda4-4983-a66d-b68557e89de4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486460925 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.486460925
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1062728859
Short name T759
Test name
Test status
Simulation time 94741898 ps
CPU time 2.52 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 197568 kb
Host smart-3b0a6e6c-4135-43e5-8324-dc003ca5cb8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062728859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1062728859
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.638059481
Short name T37
Test name
Test status
Simulation time 55271988 ps
CPU time 0.92 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 197316 kb
Host smart-b7a8d02a-73d0-4f65-b1e4-dd0b1ef430f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638059481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.638059481
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3228545454
Short name T762
Test name
Test status
Simulation time 90269333 ps
CPU time 0.79 seconds
Started Apr 25 12:32:57 PM PDT 24
Finished Apr 25 12:32:58 PM PDT 24
Peak memory 197436 kb
Host smart-dc5b49c2-8d4f-4d11-b43a-1c250acbc61b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228545454 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3228545454
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2949093588
Short name T88
Test name
Test status
Simulation time 23831900 ps
CPU time 0.64 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:02 PM PDT 24
Peak memory 194808 kb
Host smart-75f8ac07-c0b4-4084-9af6-834778300677
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949093588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2949093588
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1925143551
Short name T736
Test name
Test status
Simulation time 63702276 ps
CPU time 0.6 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 193260 kb
Host smart-63b9dbde-f6b0-4349-a9f5-b19ca519025f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925143551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1925143551
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2155986189
Short name T102
Test name
Test status
Simulation time 65984856 ps
CPU time 0.87 seconds
Started Apr 25 12:32:57 PM PDT 24
Finished Apr 25 12:32:58 PM PDT 24
Peak memory 195792 kb
Host smart-3e3249a4-b18e-4349-9a02-73808cef6e63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155986189 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2155986189
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1730989038
Short name T840
Test name
Test status
Simulation time 528267704 ps
CPU time 2.53 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:02 PM PDT 24
Peak memory 197548 kb
Host smart-130ca20a-460a-4de0-9efd-5b6db515ccd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730989038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1730989038
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1040443569
Short name T36
Test name
Test status
Simulation time 144649972 ps
CPU time 1.12 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 197708 kb
Host smart-c63e20a7-5a72-4687-bd7e-903a03b89b2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040443569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1040443569
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1504319075
Short name T734
Test name
Test status
Simulation time 68613596 ps
CPU time 1.07 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 197412 kb
Host smart-e3679da5-42df-4e2f-babe-2b8b14f6e110
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504319075 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1504319075
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2625156539
Short name T828
Test name
Test status
Simulation time 61036498 ps
CPU time 0.58 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:02 PM PDT 24
Peak memory 193452 kb
Host smart-f5cd4f17-dcbe-4643-bb91-b40b88dabc7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625156539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2625156539
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3221068097
Short name T833
Test name
Test status
Simulation time 13926091 ps
CPU time 0.57 seconds
Started Apr 25 12:33:06 PM PDT 24
Finished Apr 25 12:33:09 PM PDT 24
Peak memory 193848 kb
Host smart-a1351bce-407c-4ba5-b684-8ae77c4fb877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221068097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3221068097
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2089756589
Short name T837
Test name
Test status
Simulation time 71301886 ps
CPU time 0.83 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 195700 kb
Host smart-7a29b534-dc52-4c33-8c6a-0aa6c9ca07c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089756589 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2089756589
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1263477967
Short name T780
Test name
Test status
Simulation time 30606960 ps
CPU time 1.01 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 197480 kb
Host smart-f2090730-446b-4dd9-a8b4-92392983e7f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263477967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1263477967
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2540916171
Short name T809
Test name
Test status
Simulation time 136800161 ps
CPU time 0.82 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 197452 kb
Host smart-b356407b-83fb-42de-93bb-43ad94535883
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540916171 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2540916171
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2073384301
Short name T806
Test name
Test status
Simulation time 23672496 ps
CPU time 0.65 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 194928 kb
Host smart-3b788305-2d3a-4ab9-b894-4fcdb46ad2f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073384301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2073384301
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.336562023
Short name T732
Test name
Test status
Simulation time 43907718 ps
CPU time 0.6 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:01 PM PDT 24
Peak memory 193252 kb
Host smart-2444c88b-331e-47fc-b114-d8af2e75f7b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336562023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.336562023
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.611552316
Short name T87
Test name
Test status
Simulation time 136294021 ps
CPU time 0.74 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:05 PM PDT 24
Peak memory 195472 kb
Host smart-f9a17aae-b285-4fcd-af93-78963dceb059
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611552316 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.611552316
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1610091004
Short name T776
Test name
Test status
Simulation time 579377502 ps
CPU time 1.96 seconds
Started Apr 25 12:32:57 PM PDT 24
Finished Apr 25 12:33:01 PM PDT 24
Peak memory 197604 kb
Host smart-bd8f5c7f-e771-4250-9682-2fe2d940bcb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610091004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1610091004
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.682260514
Short name T35
Test name
Test status
Simulation time 377519113 ps
CPU time 1.45 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:02 PM PDT 24
Peak memory 197556 kb
Host smart-94c2683a-6551-40af-87e6-2c71a5d5e128
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682260514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.682260514
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.717484626
Short name T778
Test name
Test status
Simulation time 80684116 ps
CPU time 0.95 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:01 PM PDT 24
Peak memory 197416 kb
Host smart-331c52fb-b366-4523-9d3f-c34d343d668b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717484626 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.717484626
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.652947406
Short name T766
Test name
Test status
Simulation time 27679605 ps
CPU time 0.62 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 194720 kb
Host smart-1a22320b-5dbf-4fe8-8af7-1dfb5f65a64f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652947406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.652947406
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2010413045
Short name T827
Test name
Test status
Simulation time 45898054 ps
CPU time 0.58 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:01 PM PDT 24
Peak memory 193196 kb
Host smart-2693d4b7-66db-4883-89b6-e9135580dac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010413045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2010413045
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2658497526
Short name T105
Test name
Test status
Simulation time 46596544 ps
CPU time 0.63 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 193976 kb
Host smart-2146f57c-fcad-4f62-80b0-bb789e69b037
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658497526 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2658497526
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2452256043
Short name T740
Test name
Test status
Simulation time 149391650 ps
CPU time 2.54 seconds
Started Apr 25 12:33:07 PM PDT 24
Finished Apr 25 12:33:12 PM PDT 24
Peak memory 197472 kb
Host smart-d11328bd-7f05-4f26-8d30-6dbb06951bda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452256043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2452256043
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.43071811
Short name T768
Test name
Test status
Simulation time 127450090 ps
CPU time 1.67 seconds
Started Apr 25 12:33:09 PM PDT 24
Finished Apr 25 12:33:12 PM PDT 24
Peak memory 197692 kb
Host smart-e2158845-4593-4146-b8a1-8b8ecd41bcc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43071811 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.43071811
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3861088839
Short name T109
Test name
Test status
Simulation time 25013861 ps
CPU time 0.57 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:06 PM PDT 24
Peak memory 193208 kb
Host smart-1bb63000-e779-42d4-8c6d-8ad5984aba4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861088839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3861088839
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3560881161
Short name T791
Test name
Test status
Simulation time 131005821 ps
CPU time 0.63 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 193188 kb
Host smart-a268a0cb-603b-4b86-9616-50cce50b6b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560881161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3560881161
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.89533941
Short name T826
Test name
Test status
Simulation time 32714520 ps
CPU time 0.84 seconds
Started Apr 25 12:33:04 PM PDT 24
Finished Apr 25 12:33:08 PM PDT 24
Peak memory 195924 kb
Host smart-cd47bfef-7726-4c14-92d0-36347b0a2a62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89533941 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.gpio_same_csr_outstanding.89533941
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.471664446
Short name T836
Test name
Test status
Simulation time 47332130 ps
CPU time 1.1 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 197424 kb
Host smart-4bd55236-e7ac-4e35-a05b-bfa1a374b5f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471664446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.471664446
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2929832391
Short name T53
Test name
Test status
Simulation time 71267174 ps
CPU time 1.19 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 197508 kb
Host smart-6bed0a9a-516b-464d-ba64-c8ae7c4ec220
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929832391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2929832391
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.4184452705
Short name T747
Test name
Test status
Simulation time 56971305 ps
CPU time 0.94 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 197388 kb
Host smart-dd833091-3cd3-42d2-ab31-97955f4624c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184452705 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.4184452705
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1441668799
Short name T95
Test name
Test status
Simulation time 12317163 ps
CPU time 0.62 seconds
Started Apr 25 12:33:03 PM PDT 24
Finished Apr 25 12:33:08 PM PDT 24
Peak memory 194352 kb
Host smart-865debd0-176d-44b5-ab78-778421d47add
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441668799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1441668799
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1123327630
Short name T810
Test name
Test status
Simulation time 15738331 ps
CPU time 0.57 seconds
Started Apr 25 12:33:03 PM PDT 24
Finished Apr 25 12:33:08 PM PDT 24
Peak memory 193888 kb
Host smart-3d7c8243-809c-4552-aa9f-6f9b5710e805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123327630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1123327630
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.677894511
Short name T807
Test name
Test status
Simulation time 52214838 ps
CPU time 0.73 seconds
Started Apr 25 12:33:03 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 195816 kb
Host smart-14da2bbd-4992-4973-8940-5f4ac2974f5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677894511 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.677894511
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1190519552
Short name T785
Test name
Test status
Simulation time 105570463 ps
CPU time 2.02 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:05 PM PDT 24
Peak memory 197460 kb
Host smart-ef5a0c85-c631-4aba-b218-9b15c32cdc86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190519552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1190519552
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3035890403
Short name T746
Test name
Test status
Simulation time 51617872 ps
CPU time 0.9 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 196712 kb
Host smart-5561bb1e-caf4-44d6-a328-b42ba1e0b261
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035890403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3035890403
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.884432706
Short name T92
Test name
Test status
Simulation time 31880069 ps
CPU time 0.77 seconds
Started Apr 25 12:32:41 PM PDT 24
Finished Apr 25 12:32:43 PM PDT 24
Peak memory 195416 kb
Host smart-bc6ab595-7f2c-4e36-a710-2ee79d053e45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884432706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.884432706
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1136316548
Short name T760
Test name
Test status
Simulation time 253613555 ps
CPU time 3.32 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:44 PM PDT 24
Peak memory 196296 kb
Host smart-09b5958f-3473-4d7d-948e-45c053eb4aa2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136316548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1136316548
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2303120229
Short name T90
Test name
Test status
Simulation time 19869611 ps
CPU time 0.66 seconds
Started Apr 25 12:32:36 PM PDT 24
Finished Apr 25 12:32:38 PM PDT 24
Peak memory 194536 kb
Host smart-a92c6421-9c06-46d0-9e80-fa08e78259e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303120229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2303120229
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.646757096
Short name T777
Test name
Test status
Simulation time 55835106 ps
CPU time 1.33 seconds
Started Apr 25 12:32:37 PM PDT 24
Finished Apr 25 12:32:40 PM PDT 24
Peak memory 197648 kb
Host smart-a221425a-d270-4152-a620-c983cd9fc363
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646757096 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.646757096
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2880674656
Short name T98
Test name
Test status
Simulation time 40655378 ps
CPU time 0.63 seconds
Started Apr 25 12:32:42 PM PDT 24
Finished Apr 25 12:32:44 PM PDT 24
Peak memory 194464 kb
Host smart-b08398b7-c187-4b07-8d46-ccc9c2452e2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880674656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2880674656
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.943433230
Short name T748
Test name
Test status
Simulation time 41428681 ps
CPU time 0.6 seconds
Started Apr 25 12:32:41 PM PDT 24
Finished Apr 25 12:32:43 PM PDT 24
Peak memory 193972 kb
Host smart-3c27dda4-9bdd-40ed-8f6c-b21908f6cee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943433230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.943433230
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1455251634
Short name T802
Test name
Test status
Simulation time 25033707 ps
CPU time 0.73 seconds
Started Apr 25 12:32:38 PM PDT 24
Finished Apr 25 12:32:40 PM PDT 24
Peak memory 195380 kb
Host smart-fcd47fc9-e268-4449-a685-c7634666ba50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455251634 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1455251634
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2376359254
Short name T815
Test name
Test status
Simulation time 148470364 ps
CPU time 1.19 seconds
Started Apr 25 12:32:42 PM PDT 24
Finished Apr 25 12:32:44 PM PDT 24
Peak memory 197508 kb
Host smart-6e028039-262d-43cf-abb5-77cae69fe963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376359254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2376359254
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2483922385
Short name T816
Test name
Test status
Simulation time 339654860 ps
CPU time 1.18 seconds
Started Apr 25 12:32:38 PM PDT 24
Finished Apr 25 12:32:40 PM PDT 24
Peak memory 197528 kb
Host smart-0b79ea2a-3825-4add-afcc-e0923e0653f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483922385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2483922385
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1127437120
Short name T755
Test name
Test status
Simulation time 20275074 ps
CPU time 0.62 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 193264 kb
Host smart-896267aa-eebc-4b88-9669-93674c90f1fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127437120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1127437120
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1517198818
Short name T800
Test name
Test status
Simulation time 34483812 ps
CPU time 0.6 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 193904 kb
Host smart-44de48cf-0478-4471-928e-830a3afce856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517198818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1517198818
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4167596760
Short name T764
Test name
Test status
Simulation time 19029559 ps
CPU time 0.57 seconds
Started Apr 25 12:33:32 PM PDT 24
Finished Apr 25 12:33:36 PM PDT 24
Peak memory 193924 kb
Host smart-ac6f5523-fb15-4879-9a94-d672524c1f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167596760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4167596760
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1591919564
Short name T834
Test name
Test status
Simulation time 50174030 ps
CPU time 0.6 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 193200 kb
Host smart-ed1f7c3f-3921-49b3-ab7d-892b64605d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591919564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1591919564
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3858625085
Short name T742
Test name
Test status
Simulation time 68199386 ps
CPU time 0.6 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 193900 kb
Host smart-748a69d1-4d72-46a7-9ab2-0675dde4ba10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858625085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3858625085
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.4051939442
Short name T737
Test name
Test status
Simulation time 43609007 ps
CPU time 0.57 seconds
Started Apr 25 12:33:03 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 193164 kb
Host smart-1291a9f1-ba94-4336-9b9e-1bc5454b439d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051939442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.4051939442
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3317465055
Short name T842
Test name
Test status
Simulation time 36766685 ps
CPU time 0.64 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:05 PM PDT 24
Peak memory 193132 kb
Host smart-efcf695a-6817-48a9-8087-ded88c99bcd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317465055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3317465055
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.435402748
Short name T839
Test name
Test status
Simulation time 17677638 ps
CPU time 0.63 seconds
Started Apr 25 12:33:00 PM PDT 24
Finished Apr 25 12:33:04 PM PDT 24
Peak memory 193820 kb
Host smart-e87352f9-de5b-440f-b30b-a0e4a3baf805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435402748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.435402748
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.733293740
Short name T808
Test name
Test status
Simulation time 31442990 ps
CPU time 0.6 seconds
Started Apr 25 12:33:04 PM PDT 24
Finished Apr 25 12:33:08 PM PDT 24
Peak memory 193244 kb
Host smart-ac450e2d-e33b-4fc1-ba82-4d791b1bc9e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733293740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.733293740
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2075314590
Short name T775
Test name
Test status
Simulation time 24417329 ps
CPU time 0.58 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:03 PM PDT 24
Peak memory 193900 kb
Host smart-5dee6287-08f7-4976-b818-da4e5684e5d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075314590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2075314590
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2587127663
Short name T91
Test name
Test status
Simulation time 29709856 ps
CPU time 0.8 seconds
Started Apr 25 12:32:38 PM PDT 24
Finished Apr 25 12:32:40 PM PDT 24
Peak memory 195196 kb
Host smart-aee9a0fa-70e4-4c62-9f71-da6b9a2b9d00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587127663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2587127663
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.324935650
Short name T99
Test name
Test status
Simulation time 296226895 ps
CPU time 3.03 seconds
Started Apr 25 12:32:43 PM PDT 24
Finished Apr 25 12:32:47 PM PDT 24
Peak memory 197472 kb
Host smart-5c3c3dd5-9423-4223-a3f7-b0a476c84806
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324935650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.324935650
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1879349312
Short name T799
Test name
Test status
Simulation time 17829853 ps
CPU time 0.61 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:42 PM PDT 24
Peak memory 194948 kb
Host smart-06ca281e-99f6-47c5-a195-fca4b6eae828
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879349312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1879349312
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4051909918
Short name T751
Test name
Test status
Simulation time 19547802 ps
CPU time 0.67 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:42 PM PDT 24
Peak memory 197432 kb
Host smart-bc924220-eb53-4faf-b2ec-4e4d83759423
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051909918 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4051909918
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1443881962
Short name T757
Test name
Test status
Simulation time 10531534 ps
CPU time 0.58 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:41 PM PDT 24
Peak memory 194832 kb
Host smart-458aec1b-8588-4239-87cb-eb299458c6da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443881962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1443881962
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.408305399
Short name T758
Test name
Test status
Simulation time 13846593 ps
CPU time 0.68 seconds
Started Apr 25 12:32:42 PM PDT 24
Finished Apr 25 12:32:44 PM PDT 24
Peak memory 193200 kb
Host smart-2ef3f7c4-4a49-4181-b40c-85c16d3068d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408305399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.408305399
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.694181511
Short name T832
Test name
Test status
Simulation time 24513557 ps
CPU time 0.64 seconds
Started Apr 25 12:32:38 PM PDT 24
Finished Apr 25 12:32:39 PM PDT 24
Peak memory 194460 kb
Host smart-f505f274-802b-4047-8111-11197eb5916f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694181511 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.694181511
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1758869167
Short name T821
Test name
Test status
Simulation time 751266749 ps
CPU time 2.97 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:44 PM PDT 24
Peak memory 197544 kb
Host smart-1fd02a58-9f36-4c40-ad50-5762deb25e18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758869167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1758869167
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3957610114
Short name T54
Test name
Test status
Simulation time 75849875 ps
CPU time 1.2 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:43 PM PDT 24
Peak memory 197568 kb
Host smart-e8bcd8c1-ffe9-41ac-bcb7-cbdabcb2862b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957610114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3957610114
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2070919393
Short name T750
Test name
Test status
Simulation time 14565674 ps
CPU time 0.58 seconds
Started Apr 25 12:33:03 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 193144 kb
Host smart-4a7fb14f-7fdb-4187-b954-0ae098e92fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070919393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2070919393
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1605954974
Short name T796
Test name
Test status
Simulation time 12234617 ps
CPU time 0.59 seconds
Started Apr 25 12:33:03 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 193188 kb
Host smart-9c05d586-d696-4758-99f2-e35e27a70030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605954974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1605954974
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.562501800
Short name T788
Test name
Test status
Simulation time 41587052 ps
CPU time 0.58 seconds
Started Apr 25 12:33:03 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 193264 kb
Host smart-43b76fa9-c884-4d19-be52-c70f59af6205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562501800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.562501800
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3438003326
Short name T841
Test name
Test status
Simulation time 44663608 ps
CPU time 0.62 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:05 PM PDT 24
Peak memory 193332 kb
Host smart-9199a5df-e165-4f3f-8ff8-21586d395e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438003326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3438003326
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.752566036
Short name T763
Test name
Test status
Simulation time 17356267 ps
CPU time 0.64 seconds
Started Apr 25 12:33:04 PM PDT 24
Finished Apr 25 12:33:08 PM PDT 24
Peak memory 193236 kb
Host smart-fb291675-e099-425f-86da-9434afa55dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752566036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.752566036
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.26136944
Short name T772
Test name
Test status
Simulation time 52544777 ps
CPU time 0.61 seconds
Started Apr 25 12:33:06 PM PDT 24
Finished Apr 25 12:33:09 PM PDT 24
Peak memory 193164 kb
Host smart-67042a54-2793-4942-b072-4a05e9688e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26136944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.26136944
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2782045031
Short name T754
Test name
Test status
Simulation time 197475698 ps
CPU time 0.57 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:33:09 PM PDT 24
Peak memory 193128 kb
Host smart-767e429c-cf9f-4177-b7de-872dc8b23833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782045031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2782045031
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4249132784
Short name T803
Test name
Test status
Simulation time 14132866 ps
CPU time 0.58 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:13 PM PDT 24
Peak memory 193164 kb
Host smart-789bd2ed-0656-4e7a-a703-52ad2e856af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249132784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4249132784
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2774737785
Short name T845
Test name
Test status
Simulation time 48261925 ps
CPU time 0.6 seconds
Started Apr 25 12:33:06 PM PDT 24
Finished Apr 25 12:33:09 PM PDT 24
Peak memory 193240 kb
Host smart-f6090737-d54b-46e7-80b0-7a18bae9ec88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774737785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2774737785
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2919512690
Short name T752
Test name
Test status
Simulation time 13259488 ps
CPU time 0.6 seconds
Started Apr 25 12:33:03 PM PDT 24
Finished Apr 25 12:33:07 PM PDT 24
Peak memory 193944 kb
Host smart-bed2e579-0c89-46d0-83a4-06611086eb14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919512690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2919512690
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1731108323
Short name T89
Test name
Test status
Simulation time 52243406 ps
CPU time 0.78 seconds
Started Apr 25 12:32:37 PM PDT 24
Finished Apr 25 12:32:40 PM PDT 24
Peak memory 196232 kb
Host smart-bb795aaf-1279-4b3c-bd8b-f89a340dcfc8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731108323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1731108323
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2248632519
Short name T93
Test name
Test status
Simulation time 1052106662 ps
CPU time 2.13 seconds
Started Apr 25 12:32:51 PM PDT 24
Finished Apr 25 12:32:55 PM PDT 24
Peak memory 196632 kb
Host smart-d1ed0d41-ac9d-43c4-b8d7-17c14dfc3220
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248632519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2248632519
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1805594993
Short name T96
Test name
Test status
Simulation time 20922764 ps
CPU time 0.66 seconds
Started Apr 25 12:32:52 PM PDT 24
Finished Apr 25 12:32:54 PM PDT 24
Peak memory 194396 kb
Host smart-6a7ad35b-d03c-46c4-a125-4a069a7e2cad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805594993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1805594993
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.385381535
Short name T770
Test name
Test status
Simulation time 61945036 ps
CPU time 0.87 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:41 PM PDT 24
Peak memory 197408 kb
Host smart-802ee2c9-518f-478b-adaf-e73ab205bc47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385381535 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.385381535
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.881153907
Short name T101
Test name
Test status
Simulation time 19975657 ps
CPU time 0.61 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:41 PM PDT 24
Peak memory 195232 kb
Host smart-17a29432-1ec9-45ba-bfc3-2c1b96643951
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881153907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.881153907
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.30876239
Short name T793
Test name
Test status
Simulation time 12827744 ps
CPU time 0.57 seconds
Started Apr 25 12:32:39 PM PDT 24
Finished Apr 25 12:32:42 PM PDT 24
Peak memory 193084 kb
Host smart-20803249-9c23-42cc-9fc3-bb97fc705a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30876239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.30876239
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2644901730
Short name T106
Test name
Test status
Simulation time 26902642 ps
CPU time 0.73 seconds
Started Apr 25 12:32:40 PM PDT 24
Finished Apr 25 12:32:42 PM PDT 24
Peak memory 194700 kb
Host smart-fb5e3c85-74c5-4487-838a-69e2f66719db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644901730 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2644901730
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2757133044
Short name T817
Test name
Test status
Simulation time 84609859 ps
CPU time 1.72 seconds
Started Apr 25 12:32:38 PM PDT 24
Finished Apr 25 12:32:40 PM PDT 24
Peak memory 197544 kb
Host smart-2b635978-4d95-4710-86d4-69733478d509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757133044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2757133044
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.371219764
Short name T40
Test name
Test status
Simulation time 384716174 ps
CPU time 1.5 seconds
Started Apr 25 12:32:40 PM PDT 24
Finished Apr 25 12:32:43 PM PDT 24
Peak memory 197588 kb
Host smart-5b036aad-d10b-489e-b2ac-1dc9fb1ec2cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371219764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.371219764
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2992362917
Short name T843
Test name
Test status
Simulation time 128242697 ps
CPU time 0.57 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:33:09 PM PDT 24
Peak memory 193804 kb
Host smart-9220620a-d4ac-49b2-996a-a27c7d4a0772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992362917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2992362917
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.962103490
Short name T733
Test name
Test status
Simulation time 30194234 ps
CPU time 0.63 seconds
Started Apr 25 12:33:04 PM PDT 24
Finished Apr 25 12:33:08 PM PDT 24
Peak memory 193204 kb
Host smart-e5443940-6019-400d-aab5-844718fdc610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962103490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.962103490
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1988476034
Short name T801
Test name
Test status
Simulation time 24253354 ps
CPU time 0.58 seconds
Started Apr 25 12:33:06 PM PDT 24
Finished Apr 25 12:33:09 PM PDT 24
Peak memory 193144 kb
Host smart-3f5b0a63-59a7-491e-91e0-816b6eb34700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988476034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1988476034
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2617659618
Short name T779
Test name
Test status
Simulation time 176410057 ps
CPU time 0.56 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:05 PM PDT 24
Peak memory 193192 kb
Host smart-72313e75-c134-4bb6-aaff-bfed65c9205b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617659618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2617659618
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1961910079
Short name T738
Test name
Test status
Simulation time 55428701 ps
CPU time 0.59 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:13 PM PDT 24
Peak memory 193252 kb
Host smart-37b5379a-bdbe-4ebb-a7cb-97217220b18e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961910079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1961910079
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3072830487
Short name T789
Test name
Test status
Simulation time 112903223 ps
CPU time 0.64 seconds
Started Apr 25 12:33:06 PM PDT 24
Finished Apr 25 12:33:09 PM PDT 24
Peak memory 193188 kb
Host smart-45423f2b-b16a-4754-a89b-b7c9d3f77921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072830487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3072830487
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1707863260
Short name T741
Test name
Test status
Simulation time 13879869 ps
CPU time 0.56 seconds
Started Apr 25 12:33:08 PM PDT 24
Finished Apr 25 12:33:10 PM PDT 24
Peak memory 193296 kb
Host smart-6f08f2cd-cfa2-4ca3-b0df-5cf9df54b031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707863260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1707863260
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2526751577
Short name T739
Test name
Test status
Simulation time 20455877 ps
CPU time 0.61 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:33:09 PM PDT 24
Peak memory 193156 kb
Host smart-c739096a-6889-4011-b193-9147250050c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526751577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2526751577
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1986305877
Short name T773
Test name
Test status
Simulation time 12954558 ps
CPU time 0.63 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:05 PM PDT 24
Peak memory 193220 kb
Host smart-e2dbe6ee-8477-42c0-9094-f84a48e80a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986305877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1986305877
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2429117810
Short name T769
Test name
Test status
Simulation time 17979062 ps
CPU time 0.56 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:33:09 PM PDT 24
Peak memory 193336 kb
Host smart-7697e6d6-1f06-417d-a21e-de2c0f1e9b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429117810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2429117810
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3132792360
Short name T795
Test name
Test status
Simulation time 26665643 ps
CPU time 0.74 seconds
Started Apr 25 12:32:52 PM PDT 24
Finished Apr 25 12:32:54 PM PDT 24
Peak memory 197164 kb
Host smart-415fbdae-57da-4e19-b88c-0700cc9eaaba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132792360 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3132792360
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3637308991
Short name T811
Test name
Test status
Simulation time 26017413 ps
CPU time 0.66 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:50 PM PDT 24
Peak memory 194360 kb
Host smart-68849c37-5240-4489-8e1a-d709389b5137
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637308991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3637308991
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.582758776
Short name T823
Test name
Test status
Simulation time 28276768 ps
CPU time 0.6 seconds
Started Apr 25 12:32:50 PM PDT 24
Finished Apr 25 12:32:52 PM PDT 24
Peak memory 193204 kb
Host smart-6d864b05-2b24-4142-a3fa-b4a108f3560c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582758776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.582758776
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.209226971
Short name T838
Test name
Test status
Simulation time 105354313 ps
CPU time 0.8 seconds
Started Apr 25 12:32:51 PM PDT 24
Finished Apr 25 12:32:53 PM PDT 24
Peak memory 196484 kb
Host smart-9485d5e5-aaf1-490d-8952-9a4b49631d89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209226971 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.209226971
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.471612094
Short name T728
Test name
Test status
Simulation time 280744043 ps
CPU time 1.62 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:51 PM PDT 24
Peak memory 197528 kb
Host smart-28f7ea01-e480-439f-aab1-757e94102024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471612094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.471612094
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3490302467
Short name T112
Test name
Test status
Simulation time 327532767 ps
CPU time 1.09 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:49 PM PDT 24
Peak memory 197500 kb
Host smart-55326021-37e1-436f-bd4d-16742810f90d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490302467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3490302467
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3699557258
Short name T782
Test name
Test status
Simulation time 26424493 ps
CPU time 1.15 seconds
Started Apr 25 12:32:49 PM PDT 24
Finished Apr 25 12:32:51 PM PDT 24
Peak memory 197640 kb
Host smart-060b3701-ccef-40a4-a3b0-570dcde9ca02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699557258 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3699557258
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1036049359
Short name T792
Test name
Test status
Simulation time 41620206 ps
CPU time 0.66 seconds
Started Apr 25 12:32:49 PM PDT 24
Finished Apr 25 12:32:51 PM PDT 24
Peak memory 195208 kb
Host smart-99da362e-77c5-4fc8-bc3f-67f3d8c6ef71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036049359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1036049359
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2311278484
Short name T825
Test name
Test status
Simulation time 13053964 ps
CPU time 0.6 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:50 PM PDT 24
Peak memory 193196 kb
Host smart-4ca3eda3-ae82-4e23-a1f8-a2e8d912f7f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311278484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2311278484
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3949828917
Short name T798
Test name
Test status
Simulation time 117259434 ps
CPU time 0.8 seconds
Started Apr 25 12:32:59 PM PDT 24
Finished Apr 25 12:33:02 PM PDT 24
Peak memory 196272 kb
Host smart-762f49f6-e923-4b14-b008-cd8f6bcb2bf3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949828917 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3949828917
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.320324627
Short name T731
Test name
Test status
Simulation time 292735547 ps
CPU time 2.67 seconds
Started Apr 25 12:32:51 PM PDT 24
Finished Apr 25 12:32:55 PM PDT 24
Peak memory 197488 kb
Host smart-e047b36d-8b21-4f54-8d6a-c6093e5682e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320324627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.320324627
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3558533035
Short name T820
Test name
Test status
Simulation time 190690392 ps
CPU time 0.83 seconds
Started Apr 25 12:32:50 PM PDT 24
Finished Apr 25 12:32:52 PM PDT 24
Peak memory 197436 kb
Host smart-9d5838e3-92a8-4ff5-8fda-e6c264b76e97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558533035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3558533035
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4278533316
Short name T818
Test name
Test status
Simulation time 22828046 ps
CPU time 0.78 seconds
Started Apr 25 12:32:50 PM PDT 24
Finished Apr 25 12:32:52 PM PDT 24
Peak memory 197484 kb
Host smart-c842c6e8-70b6-4798-8be6-35e53c79aff1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278533316 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4278533316
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1188910376
Short name T822
Test name
Test status
Simulation time 15792927 ps
CPU time 0.64 seconds
Started Apr 25 12:32:49 PM PDT 24
Finished Apr 25 12:32:51 PM PDT 24
Peak memory 194188 kb
Host smart-c15b6e92-b116-45c6-a36b-d88305b198b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188910376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1188910376
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3938600765
Short name T814
Test name
Test status
Simulation time 18273443 ps
CPU time 0.66 seconds
Started Apr 25 12:32:51 PM PDT 24
Finished Apr 25 12:32:53 PM PDT 24
Peak memory 193876 kb
Host smart-447fdd34-5bd5-4676-996c-110f92916302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938600765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3938600765
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2541350163
Short name T103
Test name
Test status
Simulation time 14572515 ps
CPU time 0.68 seconds
Started Apr 25 12:32:50 PM PDT 24
Finished Apr 25 12:32:52 PM PDT 24
Peak memory 194628 kb
Host smart-e18d89be-7186-4cab-8f2d-bce1a3af5a07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541350163 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2541350163
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.510119764
Short name T824
Test name
Test status
Simulation time 256559041 ps
CPU time 1.52 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:51 PM PDT 24
Peak memory 197516 kb
Host smart-566cf140-f7d0-4d6c-ba72-5f6ceed643c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510119764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.510119764
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3329413624
Short name T790
Test name
Test status
Simulation time 112747197 ps
CPU time 0.83 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:50 PM PDT 24
Peak memory 197356 kb
Host smart-a722e528-db22-4bf2-9188-74d91bab3109
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329413624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3329413624
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2060540278
Short name T787
Test name
Test status
Simulation time 27397431 ps
CPU time 0.66 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:50 PM PDT 24
Peak memory 196500 kb
Host smart-7981980c-1417-4307-8b4c-a5afe9687df5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060540278 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2060540278
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1729796330
Short name T86
Test name
Test status
Simulation time 31199288 ps
CPU time 0.56 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:49 PM PDT 24
Peak memory 193436 kb
Host smart-149077e0-c718-40ff-98b4-61f75a4c1e26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729796330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1729796330
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2754476699
Short name T783
Test name
Test status
Simulation time 34040300 ps
CPU time 0.62 seconds
Started Apr 25 12:32:50 PM PDT 24
Finished Apr 25 12:32:51 PM PDT 24
Peak memory 193276 kb
Host smart-37c125fc-f694-4f31-9c5f-7d91acc98bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754476699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2754476699
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3449977203
Short name T107
Test name
Test status
Simulation time 33541645 ps
CPU time 0.8 seconds
Started Apr 25 12:32:51 PM PDT 24
Finished Apr 25 12:32:53 PM PDT 24
Peak memory 196476 kb
Host smart-87edbb81-06b1-4d77-8924-87d6c0837682
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449977203 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3449977203
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.502890134
Short name T844
Test name
Test status
Simulation time 59496119 ps
CPU time 3.07 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:52 PM PDT 24
Peak memory 197612 kb
Host smart-a6dedc41-a32a-49e9-a73f-0ec8465def5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502890134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.502890134
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1469292677
Short name T111
Test name
Test status
Simulation time 161611475 ps
CPU time 0.86 seconds
Started Apr 25 12:32:49 PM PDT 24
Finished Apr 25 12:32:51 PM PDT 24
Peak memory 197260 kb
Host smart-f1c50a54-a080-4a97-ad2c-adcaa19ec6d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469292677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1469292677
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1898401956
Short name T730
Test name
Test status
Simulation time 30143638 ps
CPU time 1.45 seconds
Started Apr 25 12:32:47 PM PDT 24
Finished Apr 25 12:32:49 PM PDT 24
Peak memory 197620 kb
Host smart-d2723b2f-62bd-41f4-a8b1-eb54a4bd7907
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898401956 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1898401956
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2470463468
Short name T781
Test name
Test status
Simulation time 47429019 ps
CPU time 0.6 seconds
Started Apr 25 12:32:47 PM PDT 24
Finished Apr 25 12:32:48 PM PDT 24
Peak memory 194920 kb
Host smart-06c8608e-90c5-4708-80f2-8c93087bed99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470463468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2470463468
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3269167743
Short name T805
Test name
Test status
Simulation time 16766116 ps
CPU time 0.64 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:00 PM PDT 24
Peak memory 193284 kb
Host smart-7957c0a8-fa20-4064-bdbf-0c23ead643cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269167743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3269167743
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3235227705
Short name T84
Test name
Test status
Simulation time 112435851 ps
CPU time 0.83 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:50 PM PDT 24
Peak memory 196500 kb
Host smart-fe4e9713-1f5f-44ab-9d6d-f9c6f2bfae6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235227705 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3235227705
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3160807346
Short name T749
Test name
Test status
Simulation time 460754212 ps
CPU time 2.5 seconds
Started Apr 25 12:32:48 PM PDT 24
Finished Apr 25 12:32:52 PM PDT 24
Peak memory 197516 kb
Host smart-35b4e329-fd22-4eed-a08f-f5d3f6b3f149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160807346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3160807346
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1181427301
Short name T52
Test name
Test status
Simulation time 44733293 ps
CPU time 0.87 seconds
Started Apr 25 12:32:58 PM PDT 24
Finished Apr 25 12:33:02 PM PDT 24
Peak memory 196392 kb
Host smart-5460c73d-397e-4286-bfc9-f8386c8e2f01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181427301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1181427301
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2217786826
Short name T641
Test name
Test status
Simulation time 13797818 ps
CPU time 0.57 seconds
Started Apr 25 12:42:38 PM PDT 24
Finished Apr 25 12:42:40 PM PDT 24
Peak memory 193868 kb
Host smart-dc26785d-f532-4a4e-a7b2-269fd8ca9d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217786826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2217786826
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2325189236
Short name T327
Test name
Test status
Simulation time 52902426 ps
CPU time 0.63 seconds
Started Apr 25 12:42:32 PM PDT 24
Finished Apr 25 12:42:35 PM PDT 24
Peak memory 194884 kb
Host smart-df8530a6-2ea5-4d83-88b9-c0e5c342fad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325189236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2325189236
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3133010820
Short name T691
Test name
Test status
Simulation time 1109517238 ps
CPU time 18.54 seconds
Started Apr 25 12:42:42 PM PDT 24
Finished Apr 25 12:43:02 PM PDT 24
Peak memory 196820 kb
Host smart-7e5b019e-c06b-447a-94ad-4b5fc6f363e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133010820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3133010820
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1491065635
Short name T30
Test name
Test status
Simulation time 75627977 ps
CPU time 0.73 seconds
Started Apr 25 12:42:37 PM PDT 24
Finished Apr 25 12:42:39 PM PDT 24
Peak memory 194872 kb
Host smart-8d4b948c-893d-44f8-bbcf-adcc005c6cfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491065635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1491065635
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3418792093
Short name T584
Test name
Test status
Simulation time 35233698 ps
CPU time 1.08 seconds
Started Apr 25 12:42:32 PM PDT 24
Finished Apr 25 12:42:35 PM PDT 24
Peak memory 196096 kb
Host smart-85fa1b97-46be-4914-abe1-a31107df56f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418792093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3418792093
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1033050925
Short name T330
Test name
Test status
Simulation time 116142589 ps
CPU time 2.28 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 198044 kb
Host smart-369ab255-5d75-4a1c-93e3-2a7b4d6c84e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033050925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1033050925
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1956313771
Short name T723
Test name
Test status
Simulation time 386215802 ps
CPU time 2.26 seconds
Started Apr 25 12:42:37 PM PDT 24
Finished Apr 25 12:42:41 PM PDT 24
Peak memory 197212 kb
Host smart-a9445f70-78d3-4572-8ebb-70ed409403fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956313771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1956313771
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1718061101
Short name T491
Test name
Test status
Simulation time 32208311 ps
CPU time 1.19 seconds
Started Apr 25 12:42:32 PM PDT 24
Finished Apr 25 12:42:35 PM PDT 24
Peak memory 196952 kb
Host smart-5eeb0293-54a1-4f78-b507-b1a0cf21bac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718061101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1718061101
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2831669534
Short name T660
Test name
Test status
Simulation time 96720206 ps
CPU time 0.71 seconds
Started Apr 25 12:42:40 PM PDT 24
Finished Apr 25 12:42:43 PM PDT 24
Peak memory 195436 kb
Host smart-f7044e6a-b703-4e2c-a377-8d3f63cf4e20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831669534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2831669534
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.348723046
Short name T475
Test name
Test status
Simulation time 178098874 ps
CPU time 2.86 seconds
Started Apr 25 12:42:36 PM PDT 24
Finished Apr 25 12:42:40 PM PDT 24
Peak memory 198020 kb
Host smart-08b544ff-7018-4979-8e83-c2334d7c1d68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348723046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.348723046
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1466664041
Short name T56
Test name
Test status
Simulation time 342464690 ps
CPU time 1.06 seconds
Started Apr 25 12:42:35 PM PDT 24
Finished Apr 25 12:42:37 PM PDT 24
Peak memory 215012 kb
Host smart-36359d7c-13bb-4a75-9cb2-8151637c87cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466664041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1466664041
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.663754758
Short name T679
Test name
Test status
Simulation time 27691405 ps
CPU time 0.89 seconds
Started Apr 25 12:42:29 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 196204 kb
Host smart-e4846055-5d64-470e-bc22-491f9aea0384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663754758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.663754758
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.343388121
Short name T596
Test name
Test status
Simulation time 158446784 ps
CPU time 1.02 seconds
Started Apr 25 12:42:32 PM PDT 24
Finished Apr 25 12:42:35 PM PDT 24
Peak memory 195868 kb
Host smart-38c0cfe2-7c0d-4b84-becf-042d1024b242
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343388121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.343388121
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1633930436
Short name T627
Test name
Test status
Simulation time 17295550099 ps
CPU time 160.7 seconds
Started Apr 25 12:42:37 PM PDT 24
Finished Apr 25 12:45:20 PM PDT 24
Peak memory 198280 kb
Host smart-076dad8f-4855-4e47-972c-a1f4270f9a7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633930436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1633930436
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.485686035
Short name T609
Test name
Test status
Simulation time 15231490 ps
CPU time 0.57 seconds
Started Apr 25 12:42:49 PM PDT 24
Finished Apr 25 12:42:52 PM PDT 24
Peak memory 194100 kb
Host smart-8c55790e-de41-4956-b877-6e90419533bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485686035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.485686035
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3811043579
Short name T379
Test name
Test status
Simulation time 53208636 ps
CPU time 0.94 seconds
Started Apr 25 12:42:40 PM PDT 24
Finished Apr 25 12:42:42 PM PDT 24
Peak memory 195968 kb
Host smart-61d75b4a-7959-4540-80f8-f9e26b8713fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811043579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3811043579
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1769469151
Short name T634
Test name
Test status
Simulation time 620258607 ps
CPU time 25.92 seconds
Started Apr 25 12:42:37 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 195580 kb
Host smart-4ba9e950-ec3f-40c3-bb51-4c8a7e5999c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769469151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1769469151
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.893945285
Short name T325
Test name
Test status
Simulation time 222815035 ps
CPU time 0.86 seconds
Started Apr 25 12:42:38 PM PDT 24
Finished Apr 25 12:42:41 PM PDT 24
Peak memory 195980 kb
Host smart-17fa13fb-fcb0-4d5d-b933-923bb51cd7bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893945285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.893945285
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2039445572
Short name T155
Test name
Test status
Simulation time 41984521 ps
CPU time 0.89 seconds
Started Apr 25 12:42:37 PM PDT 24
Finished Apr 25 12:42:40 PM PDT 24
Peak memory 196620 kb
Host smart-018c2a82-5d24-407f-b982-7428369a67a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039445572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2039445572
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3881748814
Short name T61
Test name
Test status
Simulation time 352090791 ps
CPU time 3.53 seconds
Started Apr 25 12:42:36 PM PDT 24
Finished Apr 25 12:42:40 PM PDT 24
Peak memory 197992 kb
Host smart-49241f4d-5f32-448b-8394-df2c15ca33b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881748814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3881748814
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.342772026
Short name T649
Test name
Test status
Simulation time 97824424 ps
CPU time 2.81 seconds
Started Apr 25 12:42:37 PM PDT 24
Finished Apr 25 12:42:41 PM PDT 24
Peak memory 196616 kb
Host smart-47c36f4e-1491-46f4-8033-d385f2f7b6bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342772026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.342772026
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1844624713
Short name T119
Test name
Test status
Simulation time 57327192 ps
CPU time 0.74 seconds
Started Apr 25 12:42:38 PM PDT 24
Finished Apr 25 12:42:41 PM PDT 24
Peak memory 195412 kb
Host smart-ff2f9f63-1314-4e91-8433-88c121f00011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844624713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1844624713
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.449548112
Short name T661
Test name
Test status
Simulation time 107096879 ps
CPU time 1.06 seconds
Started Apr 25 12:42:37 PM PDT 24
Finished Apr 25 12:42:40 PM PDT 24
Peak memory 195876 kb
Host smart-b564c8d1-e511-4611-9138-f3b53d900971
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449548112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.449548112
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1383984801
Short name T448
Test name
Test status
Simulation time 215678105 ps
CPU time 3.24 seconds
Started Apr 25 12:42:36 PM PDT 24
Finished Apr 25 12:42:41 PM PDT 24
Peak memory 198008 kb
Host smart-72d3d1dd-5666-4a4a-8584-f34efa156320
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383984801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1383984801
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2470991102
Short name T42
Test name
Test status
Simulation time 167603762 ps
CPU time 0.83 seconds
Started Apr 25 12:42:46 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 213884 kb
Host smart-c25e630c-1179-412c-99b8-498377f438e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470991102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2470991102
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.465847886
Short name T666
Test name
Test status
Simulation time 90508077 ps
CPU time 0.83 seconds
Started Apr 25 12:42:38 PM PDT 24
Finished Apr 25 12:42:40 PM PDT 24
Peak memory 196004 kb
Host smart-0ddc0d53-95e9-48a6-8449-4fed6ffb9e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465847886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.465847886
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1761544722
Short name T717
Test name
Test status
Simulation time 107076138 ps
CPU time 0.96 seconds
Started Apr 25 12:42:39 PM PDT 24
Finished Apr 25 12:42:41 PM PDT 24
Peak memory 195660 kb
Host smart-391a2e02-ec38-4730-b930-d6dbeb0f6437
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761544722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1761544722
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1588999383
Short name T548
Test name
Test status
Simulation time 11225996721 ps
CPU time 156.61 seconds
Started Apr 25 12:42:37 PM PDT 24
Finished Apr 25 12:45:15 PM PDT 24
Peak memory 198220 kb
Host smart-8f26f6f7-10af-4cce-892e-b9419807c7e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588999383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1588999383
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.353889304
Short name T237
Test name
Test status
Simulation time 14364983 ps
CPU time 0.56 seconds
Started Apr 25 12:43:03 PM PDT 24
Finished Apr 25 12:43:07 PM PDT 24
Peak memory 193872 kb
Host smart-af269949-f17f-453a-87d6-3d94681443b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353889304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.353889304
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3214316891
Short name T724
Test name
Test status
Simulation time 88266236 ps
CPU time 0.67 seconds
Started Apr 25 12:43:02 PM PDT 24
Finished Apr 25 12:43:06 PM PDT 24
Peak memory 194296 kb
Host smart-e2115738-4b5f-4bd9-afbc-88df3584d05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214316891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3214316891
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1960454516
Short name T545
Test name
Test status
Simulation time 136870493 ps
CPU time 7.47 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:11 PM PDT 24
Peak memory 196964 kb
Host smart-5e5271d2-22a1-4c29-b055-8a1efe613fab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960454516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1960454516
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2451166736
Short name T4
Test name
Test status
Simulation time 174249880 ps
CPU time 0.82 seconds
Started Apr 25 12:43:18 PM PDT 24
Finished Apr 25 12:43:20 PM PDT 24
Peak memory 195796 kb
Host smart-4d04dd2a-d009-438a-9116-d9cd7da765d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451166736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2451166736
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4201098519
Short name T395
Test name
Test status
Simulation time 20065949 ps
CPU time 0.72 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:09 PM PDT 24
Peak memory 195200 kb
Host smart-33cc2275-ff2d-4b00-b6cb-c817244ad27c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201098519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4201098519
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1995086361
Short name T333
Test name
Test status
Simulation time 1186466260 ps
CPU time 3.37 seconds
Started Apr 25 12:43:02 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 198096 kb
Host smart-bbb28275-32e2-4861-b43e-077edacf1e43
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995086361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1995086361
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2892149663
Short name T266
Test name
Test status
Simulation time 262909911 ps
CPU time 1.48 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 196084 kb
Host smart-5c5aae3e-cfd0-464b-8961-11b9cac97d68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892149663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2892149663
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1850137676
Short name T462
Test name
Test status
Simulation time 150525303 ps
CPU time 0.88 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 195840 kb
Host smart-ea52787b-ed9a-47d1-8c3a-e3505fa92d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850137676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1850137676
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.946801895
Short name T602
Test name
Test status
Simulation time 184384956 ps
CPU time 1.2 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:43:13 PM PDT 24
Peak memory 197376 kb
Host smart-ac9444cf-672a-4c2b-b8b5-3fa3de8c366e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946801895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.946801895
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3354354781
Short name T677
Test name
Test status
Simulation time 1105353155 ps
CPU time 3.36 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:07 PM PDT 24
Peak memory 198044 kb
Host smart-a5a79645-8805-4342-b3e1-7cd3456c2918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354354781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3354354781
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.276606366
Short name T290
Test name
Test status
Simulation time 69026544 ps
CPU time 1.27 seconds
Started Apr 25 12:43:06 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 196268 kb
Host smart-1eb252e5-c4ff-4f95-80e4-4d1b37324d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276606366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.276606366
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2069864038
Short name T472
Test name
Test status
Simulation time 344797714 ps
CPU time 0.94 seconds
Started Apr 25 12:42:57 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 195536 kb
Host smart-a5efed29-32db-4718-a78a-8b7f8d863397
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069864038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2069864038
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2916871747
Short name T566
Test name
Test status
Simulation time 4962378117 ps
CPU time 79.8 seconds
Started Apr 25 12:43:03 PM PDT 24
Finished Apr 25 12:44:25 PM PDT 24
Peak memory 198184 kb
Host smart-58f92fbe-4e4f-49a4-8576-0e84dc632a81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916871747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2916871747
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1846064973
Short name T66
Test name
Test status
Simulation time 285940030191 ps
CPU time 1126.29 seconds
Started Apr 25 12:43:03 PM PDT 24
Finished Apr 25 01:01:53 PM PDT 24
Peak memory 206412 kb
Host smart-35593ca3-2982-4b2c-8110-951450eb08d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1846064973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1846064973
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.4014993536
Short name T398
Test name
Test status
Simulation time 45882063 ps
CPU time 0.58 seconds
Started Apr 25 12:43:12 PM PDT 24
Finished Apr 25 12:43:16 PM PDT 24
Peak memory 194132 kb
Host smart-126d7add-fda6-4c2b-bd7a-babf16c6c03b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014993536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.4014993536
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3472107178
Short name T713
Test name
Test status
Simulation time 33651114 ps
CPU time 0.89 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 197060 kb
Host smart-df97bcfe-03cd-4beb-9ffc-22d0f4737b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472107178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3472107178
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2828485078
Short name T62
Test name
Test status
Simulation time 269725507 ps
CPU time 13.78 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:18 PM PDT 24
Peak memory 196760 kb
Host smart-a5cc4ae8-35dd-450b-b1bc-8030049b9f09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828485078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2828485078
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1827325150
Short name T7
Test name
Test status
Simulation time 260577206 ps
CPU time 0.88 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:04 PM PDT 24
Peak memory 196216 kb
Host smart-522915c7-7681-4b73-af4c-cedcea2afeed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827325150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1827325150
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1203716755
Short name T489
Test name
Test status
Simulation time 127597896 ps
CPU time 1.02 seconds
Started Apr 25 12:43:09 PM PDT 24
Finished Apr 25 12:43:14 PM PDT 24
Peak memory 195792 kb
Host smart-9b226290-de61-40e9-bea9-cfb23a0004df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203716755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1203716755
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3614460487
Short name T298
Test name
Test status
Simulation time 144152148 ps
CPU time 1.57 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 196240 kb
Host smart-485b19db-b147-4339-a37e-64782471fa2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614460487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3614460487
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2406819317
Short name T555
Test name
Test status
Simulation time 215543960 ps
CPU time 2.03 seconds
Started Apr 25 12:43:03 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 196212 kb
Host smart-17da98b3-e9b1-4ad6-bdb6-740bb7a71e97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406819317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2406819317
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2225300271
Short name T134
Test name
Test status
Simulation time 58833440 ps
CPU time 1.21 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:43:13 PM PDT 24
Peak memory 196264 kb
Host smart-3cc84665-c31a-4272-9066-3c94544b4615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225300271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2225300271
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3063424783
Short name T424
Test name
Test status
Simulation time 57192211 ps
CPU time 0.88 seconds
Started Apr 25 12:43:03 PM PDT 24
Finished Apr 25 12:43:07 PM PDT 24
Peak memory 196792 kb
Host smart-0532d572-e20f-4a2e-89ff-83b8a85db6ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063424783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3063424783
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_smoke.3111149692
Short name T228
Test name
Test status
Simulation time 42866279 ps
CPU time 1.16 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:04 PM PDT 24
Peak memory 195836 kb
Host smart-e85c58d0-8838-48db-a65a-ca236e16d275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111149692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3111149692
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1036964600
Short name T331
Test name
Test status
Simulation time 121463266 ps
CPU time 0.89 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:43:12 PM PDT 24
Peak memory 196496 kb
Host smart-3b3533b6-726e-481f-ac94-dcd982641ff6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036964600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1036964600
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.427944104
Short name T386
Test name
Test status
Simulation time 46440575364 ps
CPU time 79.27 seconds
Started Apr 25 12:42:59 PM PDT 24
Finished Apr 25 12:44:20 PM PDT 24
Peak memory 198232 kb
Host smart-c53f738a-7cd9-49b0-a077-1bb6d13a3b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427944104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.427944104
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2466276544
Short name T667
Test name
Test status
Simulation time 98726381 ps
CPU time 0.58 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:03 PM PDT 24
Peak memory 193972 kb
Host smart-f40eeb26-3428-4e93-8cfc-0d875a18fcf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466276544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2466276544
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1743919591
Short name T502
Test name
Test status
Simulation time 29313486 ps
CPU time 0.93 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:04 PM PDT 24
Peak memory 195916 kb
Host smart-5b9bcba6-0c98-44ea-95a3-067edf7b0568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743919591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1743919591
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3633595455
Short name T464
Test name
Test status
Simulation time 921302235 ps
CPU time 25.32 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 197120 kb
Host smart-02308820-28c7-415d-bdd6-31a72c55fd62
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633595455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3633595455
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.157428124
Short name T334
Test name
Test status
Simulation time 100884639 ps
CPU time 0.91 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:04 PM PDT 24
Peak memory 196072 kb
Host smart-f59659ce-f8e2-497a-ab7c-98824ed9c679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157428124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.157428124
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3692195801
Short name T177
Test name
Test status
Simulation time 68279135 ps
CPU time 0.79 seconds
Started Apr 25 12:43:12 PM PDT 24
Finished Apr 25 12:43:17 PM PDT 24
Peak memory 195500 kb
Host smart-f7d6b87f-57ca-4b57-bf18-90407bff0d1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692195801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3692195801
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3898913314
Short name T322
Test name
Test status
Simulation time 54582162 ps
CPU time 2.09 seconds
Started Apr 25 12:42:58 PM PDT 24
Finished Apr 25 12:43:02 PM PDT 24
Peak memory 196320 kb
Host smart-424d27d5-3c6f-44d4-9c0c-050dd365e44b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898913314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3898913314
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1677411245
Short name T11
Test name
Test status
Simulation time 402120844 ps
CPU time 2.24 seconds
Started Apr 25 12:43:27 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 198044 kb
Host smart-a9db3f55-f24c-4886-91aa-3d744f5f1778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677411245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1677411245
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2853410539
Short name T199
Test name
Test status
Simulation time 16186509 ps
CPU time 0.67 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 195484 kb
Host smart-144a459e-84bb-427b-97d6-945c36a67122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853410539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2853410539
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3019348914
Short name T712
Test name
Test status
Simulation time 67384866 ps
CPU time 0.71 seconds
Started Apr 25 12:43:02 PM PDT 24
Finished Apr 25 12:43:06 PM PDT 24
Peak memory 196208 kb
Host smart-9906748b-192e-4f15-a5a9-9e9782ec0e5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019348914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3019348914
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3500514834
Short name T345
Test name
Test status
Simulation time 577365307 ps
CPU time 6.67 seconds
Started Apr 25 12:43:34 PM PDT 24
Finished Apr 25 12:43:42 PM PDT 24
Peak memory 198032 kb
Host smart-422afda1-b9d1-4251-83b2-acc72caeabaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500514834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3500514834
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1891125944
Short name T318
Test name
Test status
Simulation time 50783892 ps
CPU time 1.35 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 197944 kb
Host smart-70d38dfd-a678-420b-8139-513a151b60dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891125944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1891125944
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1180972483
Short name T707
Test name
Test status
Simulation time 32669691 ps
CPU time 0.87 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:03 PM PDT 24
Peak memory 196072 kb
Host smart-6f6fa8b2-9c13-42c5-b77e-874ad24ae6c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180972483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1180972483
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3470356081
Short name T640
Test name
Test status
Simulation time 48180846254 ps
CPU time 89.13 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:44:32 PM PDT 24
Peak memory 198200 kb
Host smart-a337c502-2328-4d28-b22a-40f2f4844ec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470356081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3470356081
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3194750320
Short name T495
Test name
Test status
Simulation time 43042117 ps
CPU time 0.57 seconds
Started Apr 25 12:43:06 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 193860 kb
Host smart-190e9302-e23e-451d-9cf0-a7ea3957280c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194750320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3194750320
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3740225033
Short name T191
Test name
Test status
Simulation time 61734357 ps
CPU time 0.72 seconds
Started Apr 25 12:43:03 PM PDT 24
Finished Apr 25 12:43:07 PM PDT 24
Peak memory 195356 kb
Host smart-3cfd3c16-1e5b-4a7c-bc66-0df11adf2719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740225033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3740225033
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1932309205
Short name T23
Test name
Test status
Simulation time 1953011729 ps
CPU time 18.78 seconds
Started Apr 25 12:43:02 PM PDT 24
Finished Apr 25 12:43:24 PM PDT 24
Peak memory 197028 kb
Host smart-db5862b0-8721-494d-be8c-9af29ccb3a74
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932309205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1932309205
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.621519677
Short name T562
Test name
Test status
Simulation time 37222533 ps
CPU time 0.73 seconds
Started Apr 25 12:43:16 PM PDT 24
Finished Apr 25 12:43:19 PM PDT 24
Peak memory 194736 kb
Host smart-b999381c-6379-41d3-a701-121b2dc5d242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621519677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.621519677
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2088535964
Short name T257
Test name
Test status
Simulation time 33989128 ps
CPU time 0.86 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 195996 kb
Host smart-9290f7ff-a4d7-416a-80ce-41fa440c536e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088535964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2088535964
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.710947768
Short name T332
Test name
Test status
Simulation time 77131080 ps
CPU time 3.08 seconds
Started Apr 25 12:43:02 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 198112 kb
Host smart-c9de7e9f-4b8b-4536-9c51-427939b84903
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710947768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.710947768
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.39634619
Short name T435
Test name
Test status
Simulation time 139764397 ps
CPU time 3.2 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:06 PM PDT 24
Peak memory 197032 kb
Host smart-4bedf03f-f306-4470-b352-120e1abcdbca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39634619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.39634619
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2675785062
Short name T427
Test name
Test status
Simulation time 161364623 ps
CPU time 1.05 seconds
Started Apr 25 12:43:06 PM PDT 24
Finished Apr 25 12:43:11 PM PDT 24
Peak memory 195896 kb
Host smart-1e10a9fd-58d3-4b9d-952a-df771687445b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675785062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2675785062
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.313316627
Short name T599
Test name
Test status
Simulation time 57046450 ps
CPU time 0.91 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 196692 kb
Host smart-301c9042-adf3-4284-9698-821307dc1450
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313316627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.313316627
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.772333685
Short name T715
Test name
Test status
Simulation time 1180649262 ps
CPU time 4.49 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:43:16 PM PDT 24
Peak memory 197928 kb
Host smart-bf68106c-b065-4068-9c54-cf895f2c5ab5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772333685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.772333685
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3382091415
Short name T197
Test name
Test status
Simulation time 311470175 ps
CPU time 1.31 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:09 PM PDT 24
Peak memory 197972 kb
Host smart-82a537a2-a221-4475-97e3-99a055a89435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382091415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3382091415
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3680713766
Short name T531
Test name
Test status
Simulation time 70037091 ps
CPU time 1.33 seconds
Started Apr 25 12:43:02 PM PDT 24
Finished Apr 25 12:43:06 PM PDT 24
Peak memory 197140 kb
Host smart-642d5246-07b2-44c8-ae5b-8330e611c607
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680713766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3680713766
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.556020977
Short name T5
Test name
Test status
Simulation time 36698133843 ps
CPU time 102.07 seconds
Started Apr 25 12:43:03 PM PDT 24
Finished Apr 25 12:44:49 PM PDT 24
Peak memory 198160 kb
Host smart-6ee0d5df-2091-48a4-8abf-7a184fc502be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556020977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.556020977
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3728519244
Short name T371
Test name
Test status
Simulation time 57936284754 ps
CPU time 1150.66 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 01:02:14 PM PDT 24
Peak memory 198372 kb
Host smart-19cff5b6-bab5-4c46-a8bc-548b9825300d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3728519244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3728519244
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.4273723253
Short name T526
Test name
Test status
Simulation time 11550774 ps
CPU time 0.57 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:09 PM PDT 24
Peak memory 193924 kb
Host smart-534b9537-57a6-4ff0-93b3-653f1e1ecd8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273723253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.4273723253
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4023927852
Short name T537
Test name
Test status
Simulation time 461961297 ps
CPU time 0.8 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 195488 kb
Host smart-51986732-f272-4bfc-bc96-ad581717c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023927852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4023927852
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1668560160
Short name T206
Test name
Test status
Simulation time 861570430 ps
CPU time 26.79 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:35 PM PDT 24
Peak memory 195524 kb
Host smart-bd6ddf22-e824-422d-aca3-75c41b4894b8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668560160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1668560160
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3657227146
Short name T73
Test name
Test status
Simulation time 70950084 ps
CPU time 0.88 seconds
Started Apr 25 12:43:18 PM PDT 24
Finished Apr 25 12:43:20 PM PDT 24
Peak memory 197692 kb
Host smart-ba1e5b6f-0761-424f-ab72-934d0aef3ee7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657227146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3657227146
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.57622911
Short name T114
Test name
Test status
Simulation time 77585468 ps
CPU time 1.23 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:16 PM PDT 24
Peak memory 196660 kb
Host smart-c301d26f-7c72-4453-88f8-ced2f6f1bfb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57622911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.57622911
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2786369436
Short name T719
Test name
Test status
Simulation time 146017061 ps
CPU time 2.63 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 198076 kb
Host smart-522c250c-0d31-44cf-978e-437eb471e3f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786369436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2786369436
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1509772915
Short name T402
Test name
Test status
Simulation time 139972971 ps
CPU time 1.75 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:17 PM PDT 24
Peak memory 195956 kb
Host smart-3c0910d3-a502-4705-84df-82ebf2af6e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509772915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1509772915
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3870856414
Short name T501
Test name
Test status
Simulation time 34930931 ps
CPU time 1.15 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 196652 kb
Host smart-9752e42c-77cc-4824-88fc-bb461899ec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870856414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3870856414
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1650295014
Short name T675
Test name
Test status
Simulation time 68793364 ps
CPU time 0.84 seconds
Started Apr 25 12:43:30 PM PDT 24
Finished Apr 25 12:43:33 PM PDT 24
Peak memory 196608 kb
Host smart-fb8e4d7a-699d-4b79-9ba2-1266d83a23c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650295014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1650295014
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_smoke.3344904621
Short name T646
Test name
Test status
Simulation time 34786202 ps
CPU time 0.76 seconds
Started Apr 25 12:43:03 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 194188 kb
Host smart-64951e0a-e7b7-499e-b612-79177117ebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344904621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3344904621
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1419694185
Short name T695
Test name
Test status
Simulation time 109203170 ps
CPU time 1.14 seconds
Started Apr 25 12:43:22 PM PDT 24
Finished Apr 25 12:43:25 PM PDT 24
Peak memory 196448 kb
Host smart-e72d55d9-10da-4e59-a5f5-a007fcbbf52a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419694185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1419694185
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2351545014
Short name T704
Test name
Test status
Simulation time 28871749313 ps
CPU time 100.03 seconds
Started Apr 25 12:43:07 PM PDT 24
Finished Apr 25 12:44:51 PM PDT 24
Peak memory 198236 kb
Host smart-6e7f2f61-e1b4-445d-a848-8b7293325eef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351545014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2351545014
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1043129938
Short name T360
Test name
Test status
Simulation time 17590252 ps
CPU time 0.61 seconds
Started Apr 25 12:43:27 PM PDT 24
Finished Apr 25 12:43:29 PM PDT 24
Peak memory 194212 kb
Host smart-0e430980-65e6-4f5c-b899-e3bd370d281b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043129938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1043129938
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1496825915
Short name T277
Test name
Test status
Simulation time 57510285 ps
CPU time 0.8 seconds
Started Apr 25 12:43:27 PM PDT 24
Finished Apr 25 12:43:29 PM PDT 24
Peak memory 195380 kb
Host smart-5a1b0ee0-20ce-4edd-8e97-9ec299577860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496825915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1496825915
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.819515667
Short name T465
Test name
Test status
Simulation time 1290600511 ps
CPU time 15.69 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 196892 kb
Host smart-8b81c10c-2780-4a00-b42a-830457136c8b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819515667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.819515667
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1563125507
Short name T581
Test name
Test status
Simulation time 215719179 ps
CPU time 0.81 seconds
Started Apr 25 12:43:06 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 196052 kb
Host smart-b7977433-eb96-4fdc-900b-c9e88b2caf8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563125507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1563125507
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2519233469
Short name T131
Test name
Test status
Simulation time 42027573 ps
CPU time 1.17 seconds
Started Apr 25 12:43:09 PM PDT 24
Finished Apr 25 12:43:13 PM PDT 24
Peak memory 195816 kb
Host smart-f8253fc8-24ba-4055-9b08-a18c09c25717
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519233469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2519233469
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.885404444
Short name T201
Test name
Test status
Simulation time 90621971 ps
CPU time 3.63 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:17 PM PDT 24
Peak memory 198052 kb
Host smart-32a7e63a-2595-475d-b513-33486ca3d222
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885404444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.885404444
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3233158755
Short name T541
Test name
Test status
Simulation time 50844138 ps
CPU time 1.33 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 197004 kb
Host smart-70386a77-e8f9-4e2f-82c5-64d6609dd8ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233158755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3233158755
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1717827718
Short name T343
Test name
Test status
Simulation time 65884003 ps
CPU time 0.76 seconds
Started Apr 25 12:43:09 PM PDT 24
Finished Apr 25 12:43:14 PM PDT 24
Peak memory 195480 kb
Host smart-17bb8aab-3c73-4bcb-8512-bd61b7ce1f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717827718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1717827718
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.752100005
Short name T705
Test name
Test status
Simulation time 77952716 ps
CPU time 0.94 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:09 PM PDT 24
Peak memory 196544 kb
Host smart-c4fdb99d-23de-4a59-8942-fa61ebb86f5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752100005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.752100005
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3967395276
Short name T485
Test name
Test status
Simulation time 98441037 ps
CPU time 4.44 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:11 PM PDT 24
Peak memory 198016 kb
Host smart-f18166c4-b324-4e49-8523-6a2cf0d44be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967395276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3967395276
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1683274516
Short name T320
Test name
Test status
Simulation time 75678764 ps
CPU time 0.72 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 195988 kb
Host smart-c00266b6-0e79-4e39-a84a-b198cf59faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683274516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1683274516
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.202810206
Short name T355
Test name
Test status
Simulation time 60965563 ps
CPU time 1.26 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 198052 kb
Host smart-63618ce2-c901-4f25-a3f9-fc096e2b25f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202810206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.202810206
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3162955163
Short name T10
Test name
Test status
Simulation time 10502018607 ps
CPU time 113.38 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:45:05 PM PDT 24
Peak memory 198276 kb
Host smart-c14a0cc8-15ad-432a-b795-e6da0df86a56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162955163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3162955163
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.450495191
Short name T108
Test name
Test status
Simulation time 67956583210 ps
CPU time 923.63 seconds
Started Apr 25 12:43:06 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 198272 kb
Host smart-13b0bd64-cd52-4dcf-804f-f9d9df924271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=450495191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.450495191
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.523720278
Short name T657
Test name
Test status
Simulation time 15650448 ps
CPU time 0.58 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 194080 kb
Host smart-acabd932-599a-44ae-a918-55d3be557bd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523720278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.523720278
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1901044665
Short name T645
Test name
Test status
Simulation time 47508309 ps
CPU time 0.88 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 196368 kb
Host smart-30872d9b-8133-42cd-8a61-dbe5dce13ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901044665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1901044665
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3013192717
Short name T213
Test name
Test status
Simulation time 598742721 ps
CPU time 17.86 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:32 PM PDT 24
Peak memory 198000 kb
Host smart-86b487d0-178f-4da2-9bfe-0461e6c7cfa8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013192717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3013192717
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3729583230
Short name T480
Test name
Test status
Simulation time 45992785 ps
CPU time 0.75 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 196644 kb
Host smart-f17b5fa0-2a8e-4af8-bd37-a4dacc932e14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729583230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3729583230
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1789795581
Short name T283
Test name
Test status
Simulation time 149369967 ps
CPU time 1.13 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:09 PM PDT 24
Peak memory 196120 kb
Host smart-72d87091-ac60-4e21-9a7d-a0c18057d259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789795581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1789795581
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3942373138
Short name T647
Test name
Test status
Simulation time 315398572 ps
CPU time 3.15 seconds
Started Apr 25 12:43:25 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 198116 kb
Host smart-959d03ee-8cf7-421e-897d-506aa85efdd3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942373138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3942373138
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2463350752
Short name T138
Test name
Test status
Simulation time 81511721 ps
CPU time 1.71 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 196716 kb
Host smart-ccb9a4c1-f170-48a0-a577-a41f6e26789b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463350752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2463350752
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.4288267680
Short name T436
Test name
Test status
Simulation time 52217871 ps
CPU time 1.01 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:16 PM PDT 24
Peak memory 195832 kb
Host smart-ddaa417a-5849-4e74-ac42-4af8300b8fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288267680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.4288267680
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3137572901
Short name T684
Test name
Test status
Simulation time 28707184 ps
CPU time 1.03 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 196772 kb
Host smart-1ca96762-c4bc-421a-85db-d32752e1a779
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137572901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3137572901
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1761639671
Short name T250
Test name
Test status
Simulation time 797854293 ps
CPU time 3.37 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:43:16 PM PDT 24
Peak memory 197920 kb
Host smart-e42872a1-8271-485b-9029-77eb0ca48f3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761639671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1761639671
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2230047484
Short name T651
Test name
Test status
Simulation time 38887509 ps
CPU time 0.71 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:16 PM PDT 24
Peak memory 194212 kb
Host smart-d574a12a-2e27-42eb-9ebb-c33721808116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230047484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2230047484
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3621039507
Short name T384
Test name
Test status
Simulation time 44248313 ps
CPU time 0.94 seconds
Started Apr 25 12:43:06 PM PDT 24
Finished Apr 25 12:43:10 PM PDT 24
Peak memory 196232 kb
Host smart-71a93eb2-a428-4734-99e0-cfa4bb4011d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621039507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3621039507
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2926271096
Short name T632
Test name
Test status
Simulation time 13799587248 ps
CPU time 142.23 seconds
Started Apr 25 12:43:23 PM PDT 24
Finished Apr 25 12:45:46 PM PDT 24
Peak memory 198220 kb
Host smart-168401c5-92cd-4f7b-a1f5-27a4caed5dfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926271096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2926271096
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3494363368
Short name T668
Test name
Test status
Simulation time 244194206344 ps
CPU time 599.94 seconds
Started Apr 25 12:43:17 PM PDT 24
Finished Apr 25 12:53:19 PM PDT 24
Peak memory 206500 kb
Host smart-4186b488-6435-4372-b523-5e481c5319f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3494363368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3494363368
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2751188874
Short name T643
Test name
Test status
Simulation time 46551178 ps
CPU time 0.58 seconds
Started Apr 25 12:43:24 PM PDT 24
Finished Apr 25 12:43:25 PM PDT 24
Peak memory 194884 kb
Host smart-b1e1c6d0-a9ee-437f-856f-8cfb2967899a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751188874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2751188874
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3147681135
Short name T408
Test name
Test status
Simulation time 38008717 ps
CPU time 0.77 seconds
Started Apr 25 12:43:20 PM PDT 24
Finished Apr 25 12:43:22 PM PDT 24
Peak memory 195468 kb
Host smart-6d414e25-b2c5-41ca-a4ce-db0e56d53a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147681135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3147681135
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2098909252
Short name T163
Test name
Test status
Simulation time 1315710506 ps
CPU time 17.06 seconds
Started Apr 25 12:43:09 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 196764 kb
Host smart-ab5bebf0-e078-4f2f-b834-17a32c2f60c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098909252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2098909252
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2786658886
Short name T449
Test name
Test status
Simulation time 68619465 ps
CPU time 0.61 seconds
Started Apr 25 12:43:05 PM PDT 24
Finished Apr 25 12:43:09 PM PDT 24
Peak memory 194588 kb
Host smart-77616528-e729-4067-85a3-a5098e3e0efe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786658886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2786658886
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.4254161232
Short name T292
Test name
Test status
Simulation time 70152229 ps
CPU time 1.24 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:16 PM PDT 24
Peak memory 195848 kb
Host smart-c2763068-0ac4-4c04-a476-eba8b6ff2500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254161232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.4254161232
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1172486584
Short name T383
Test name
Test status
Simulation time 84476022 ps
CPU time 3.33 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 198020 kb
Host smart-283484e7-08c5-4b5d-8820-1289cc4a5043
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172486584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1172486584
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1799065946
Short name T244
Test name
Test status
Simulation time 269647868 ps
CPU time 2.68 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:18 PM PDT 24
Peak memory 195816 kb
Host smart-508819b7-2973-40f0-8b37-933bcb2b2857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799065946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1799065946
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3675103730
Short name T160
Test name
Test status
Simulation time 248595303 ps
CPU time 1.08 seconds
Started Apr 25 12:43:21 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 196724 kb
Host smart-9e85e24e-a964-48e8-b4cf-32315ce0663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675103730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3675103730
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4046920272
Short name T614
Test name
Test status
Simulation time 41525574 ps
CPU time 1 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:43:13 PM PDT 24
Peak memory 196704 kb
Host smart-8bc0df1d-1eab-40d9-b20a-d8efb74eefa5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046920272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.4046920272
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.503234535
Short name T598
Test name
Test status
Simulation time 202175705 ps
CPU time 1.56 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:43:14 PM PDT 24
Peak memory 198032 kb
Host smart-773925af-cf88-46d2-af4a-84f46c9b1dfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503234535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.503234535
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2766676286
Short name T482
Test name
Test status
Simulation time 58303342 ps
CPU time 1.06 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 195720 kb
Host smart-88611d96-e630-4078-b45a-73412863a7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766676286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2766676286
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2557907282
Short name T425
Test name
Test status
Simulation time 102621096 ps
CPU time 1.06 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 196544 kb
Host smart-f8154070-3413-4e48-8bbb-70b0e91c71c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557907282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2557907282
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.266587389
Short name T577
Test name
Test status
Simulation time 16486442728 ps
CPU time 56 seconds
Started Apr 25 12:43:14 PM PDT 24
Finished Apr 25 12:44:14 PM PDT 24
Peak memory 198184 kb
Host smart-098e9185-7fe7-4818-8450-0b811ea0b886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266587389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.266587389
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1353408837
Short name T689
Test name
Test status
Simulation time 206789468365 ps
CPU time 1371.91 seconds
Started Apr 25 12:43:22 PM PDT 24
Finished Apr 25 01:06:15 PM PDT 24
Peak memory 198312 kb
Host smart-250c1145-7d26-4de8-b16e-c99305da7158
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1353408837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1353408837
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.4287832298
Short name T294
Test name
Test status
Simulation time 36758710 ps
CPU time 0.55 seconds
Started Apr 25 12:43:13 PM PDT 24
Finished Apr 25 12:43:17 PM PDT 24
Peak memory 192820 kb
Host smart-dc2196e5-78ec-48a3-ade5-01ac13bb5f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287832298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.4287832298
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.88786280
Short name T680
Test name
Test status
Simulation time 24554867 ps
CPU time 0.68 seconds
Started Apr 25 12:43:09 PM PDT 24
Finished Apr 25 12:43:14 PM PDT 24
Peak memory 195144 kb
Host smart-9d2f81fd-b9e8-42ac-b006-7a379086c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88786280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.88786280
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3974606161
Short name T450
Test name
Test status
Simulation time 375129003 ps
CPU time 5.61 seconds
Started Apr 25 12:43:24 PM PDT 24
Finished Apr 25 12:43:31 PM PDT 24
Peak memory 196792 kb
Host smart-d51f903d-45e4-4943-850b-40f99d08b245
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974606161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3974606161
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3276373139
Short name T396
Test name
Test status
Simulation time 29576031 ps
CPU time 0.68 seconds
Started Apr 25 12:43:36 PM PDT 24
Finished Apr 25 12:43:38 PM PDT 24
Peak memory 194840 kb
Host smart-79d4217b-0871-4ed3-8b4f-c70fa64adbb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276373139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3276373139
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1047756908
Short name T80
Test name
Test status
Simulation time 83474632 ps
CPU time 1.07 seconds
Started Apr 25 12:43:31 PM PDT 24
Finished Apr 25 12:43:34 PM PDT 24
Peak memory 195780 kb
Host smart-3dddf199-42df-4de0-bea9-661ab31c19e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047756908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1047756908
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.4072383533
Short name T17
Test name
Test status
Simulation time 371735451 ps
CPU time 3.52 seconds
Started Apr 25 12:43:20 PM PDT 24
Finished Apr 25 12:43:24 PM PDT 24
Peak memory 198032 kb
Host smart-9425b004-dcc8-47b2-b59d-7452a16c3e96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072383533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.4072383533
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4085156696
Short name T59
Test name
Test status
Simulation time 295291615 ps
CPU time 3.23 seconds
Started Apr 25 12:43:18 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 197976 kb
Host smart-42396139-1b5f-4709-b3f5-8fcea71d7a55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085156696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4085156696
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3054955781
Short name T518
Test name
Test status
Simulation time 61000549 ps
CPU time 1.36 seconds
Started Apr 25 12:43:04 PM PDT 24
Finished Apr 25 12:43:09 PM PDT 24
Peak memory 196604 kb
Host smart-de2430fb-2b4c-42bf-a179-a6399747be3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054955781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3054955781
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1878234964
Short name T588
Test name
Test status
Simulation time 80916972 ps
CPU time 0.88 seconds
Started Apr 25 12:43:19 PM PDT 24
Finished Apr 25 12:43:21 PM PDT 24
Peak memory 196672 kb
Host smart-04b13f21-0f96-4eef-a793-b8289e08f587
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878234964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1878234964
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2947528968
Short name T261
Test name
Test status
Simulation time 44942183 ps
CPU time 2.09 seconds
Started Apr 25 12:43:29 PM PDT 24
Finished Apr 25 12:43:33 PM PDT 24
Peak memory 198100 kb
Host smart-b30d9ff0-09fe-4252-a6d9-67de1d50455d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947528968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2947528968
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1912897957
Short name T370
Test name
Test status
Simulation time 131308063 ps
CPU time 0.81 seconds
Started Apr 25 12:43:08 PM PDT 24
Finished Apr 25 12:43:12 PM PDT 24
Peak memory 195408 kb
Host smart-711ba6b8-9850-4c27-819b-5c2c5956133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912897957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1912897957
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1583842934
Short name T453
Test name
Test status
Simulation time 243707952 ps
CPU time 1.22 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 195860 kb
Host smart-71c9fefd-8dd1-46fb-a21c-d27e0c16f8ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583842934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1583842934
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3559044032
Short name T193
Test name
Test status
Simulation time 1978938304 ps
CPU time 51.08 seconds
Started Apr 25 12:43:14 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 198040 kb
Host smart-e235a3f7-f5d0-49ea-b804-bf57cc29edae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559044032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3559044032
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3644063744
Short name T575
Test name
Test status
Simulation time 21519783 ps
CPU time 0.58 seconds
Started Apr 25 12:43:25 PM PDT 24
Finished Apr 25 12:43:27 PM PDT 24
Peak memory 194188 kb
Host smart-a1c07fdb-d4b5-47a8-928d-86eb88172085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644063744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3644063744
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1012548113
Short name T209
Test name
Test status
Simulation time 198819243 ps
CPU time 0.9 seconds
Started Apr 25 12:43:10 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 196708 kb
Host smart-bdb0ddca-e100-4689-b897-396d9506034a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012548113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1012548113
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.107809200
Short name T538
Test name
Test status
Simulation time 2163871130 ps
CPU time 14.19 seconds
Started Apr 25 12:43:31 PM PDT 24
Finished Apr 25 12:43:47 PM PDT 24
Peak memory 195616 kb
Host smart-e4e0cf49-b5fb-4ea6-9af4-bcbeb6f43853
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107809200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.107809200
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3010792862
Short name T219
Test name
Test status
Simulation time 57612799 ps
CPU time 0.91 seconds
Started Apr 25 12:43:24 PM PDT 24
Finished Apr 25 12:43:26 PM PDT 24
Peak memory 196188 kb
Host smart-b2c3e7c6-d7bf-4fe2-b85c-e01af2cda382
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010792862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3010792862
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.924743878
Short name T306
Test name
Test status
Simulation time 71603335 ps
CPU time 1.02 seconds
Started Apr 25 12:43:13 PM PDT 24
Finished Apr 25 12:43:18 PM PDT 24
Peak memory 196852 kb
Host smart-9591f643-dfdc-431a-b33b-1c700357e860
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924743878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.924743878
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3863645725
Short name T536
Test name
Test status
Simulation time 117523327 ps
CPU time 1.63 seconds
Started Apr 25 12:44:12 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 197900 kb
Host smart-81fac1cc-7b9e-4e8e-b157-607b18f01761
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863645725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3863645725
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1793571514
Short name T353
Test name
Test status
Simulation time 36099034 ps
CPU time 1.33 seconds
Started Apr 25 12:43:47 PM PDT 24
Finished Apr 25 12:43:49 PM PDT 24
Peak memory 197212 kb
Host smart-7655fbba-7f78-4691-b492-c79a2c70196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793571514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1793571514
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1360130483
Short name T603
Test name
Test status
Simulation time 120664324 ps
CPU time 0.81 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:39 PM PDT 24
Peak memory 195652 kb
Host smart-6e1bf645-5508-4425-b9d3-a3475884d5e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360130483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1360130483
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2726598144
Short name T543
Test name
Test status
Simulation time 70641401 ps
CPU time 1.85 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:01 PM PDT 24
Peak memory 198072 kb
Host smart-0348b9d8-7d51-40f0-8883-31b3ea7623fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726598144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2726598144
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2596118014
Short name T709
Test name
Test status
Simulation time 140191085 ps
CPU time 1.13 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 195584 kb
Host smart-bbae6af9-f894-4b35-9559-c786fa7b3c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596118014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2596118014
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2447937481
Short name T279
Test name
Test status
Simulation time 32147109 ps
CPU time 0.91 seconds
Started Apr 25 12:43:27 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 196188 kb
Host smart-d804ea82-7d8b-433a-b6e8-df35a771dd57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447937481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2447937481
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.124174502
Short name T445
Test name
Test status
Simulation time 72450130304 ps
CPU time 72.7 seconds
Started Apr 25 12:43:26 PM PDT 24
Finished Apr 25 12:44:40 PM PDT 24
Peak memory 198156 kb
Host smart-62766cbe-dfcc-4879-a6a7-dd5e5f9e8f8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124174502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.124174502
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1998984839
Short name T72
Test name
Test status
Simulation time 26655240718 ps
CPU time 664.29 seconds
Started Apr 25 12:43:21 PM PDT 24
Finished Apr 25 12:54:27 PM PDT 24
Peak memory 198188 kb
Host smart-16678fe1-050a-4ea2-87dc-a02d90f3e966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1998984839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1998984839
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3032403615
Short name T356
Test name
Test status
Simulation time 35864100 ps
CPU time 0.56 seconds
Started Apr 25 12:42:46 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 192784 kb
Host smart-137963c9-77ab-4b97-95f4-86b3de3e3bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032403615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3032403615
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3244048175
Short name T488
Test name
Test status
Simulation time 107115743 ps
CPU time 0.71 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:50 PM PDT 24
Peak memory 194896 kb
Host smart-b0fbdbd5-2672-40a7-8a58-3ac8277dbb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244048175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3244048175
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3032046668
Short name T594
Test name
Test status
Simulation time 1680120866 ps
CPU time 25.32 seconds
Started Apr 25 12:42:46 PM PDT 24
Finished Apr 25 12:43:13 PM PDT 24
Peak memory 195532 kb
Host smart-b0920457-13aa-475c-bd73-060f697d44bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032046668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3032046668
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1069653391
Short name T317
Test name
Test status
Simulation time 160582000 ps
CPU time 0.77 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:50 PM PDT 24
Peak memory 195932 kb
Host smart-2cd6b46c-f297-4f02-8b8e-a7b738baba01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069653391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1069653391
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4192692943
Short name T270
Test name
Test status
Simulation time 654757859 ps
CPU time 1.22 seconds
Started Apr 25 12:42:45 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 196120 kb
Host smart-6ad2af22-a5fa-4446-ac77-72b3391554b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192692943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4192692943
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3475851969
Short name T115
Test name
Test status
Simulation time 47229635 ps
CPU time 1.91 seconds
Started Apr 25 12:42:45 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 198052 kb
Host smart-b43b75bc-1293-4f32-9f14-4ea0c64d298f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475851969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3475851969
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.613127279
Short name T302
Test name
Test status
Simulation time 228880248 ps
CPU time 1.18 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:50 PM PDT 24
Peak memory 196684 kb
Host smart-52996bf8-7c7f-457c-a88d-e7287da6ad90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613127279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.613127279
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.651058358
Short name T246
Test name
Test status
Simulation time 205946755 ps
CPU time 0.76 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:50 PM PDT 24
Peak memory 195464 kb
Host smart-3e22a150-adc1-4d6c-8ff4-ed1f75d7e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651058358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.651058358
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1321401235
Short name T361
Test name
Test status
Simulation time 24378142 ps
CPU time 0.75 seconds
Started Apr 25 12:42:49 PM PDT 24
Finished Apr 25 12:42:52 PM PDT 24
Peak memory 194332 kb
Host smart-1f6026f4-3393-45f0-bf5c-98efe8e9db94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321401235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1321401235
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3073264322
Short name T363
Test name
Test status
Simulation time 357806576 ps
CPU time 3.97 seconds
Started Apr 25 12:42:45 PM PDT 24
Finished Apr 25 12:42:50 PM PDT 24
Peak memory 197968 kb
Host smart-44065f58-4b11-4ebf-81bf-45e790fb8faa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073264322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3073264322
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.1580830639
Short name T293
Test name
Test status
Simulation time 1231325859 ps
CPU time 1.12 seconds
Started Apr 25 12:42:45 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 196456 kb
Host smart-280edbaf-c33f-4472-9538-2b138890128b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580830639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1580830639
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1140067810
Short name T178
Test name
Test status
Simulation time 341705101 ps
CPU time 1.19 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:51 PM PDT 24
Peak memory 196540 kb
Host smart-29ca19b3-dd51-4cef-a7aa-66e20b441c94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140067810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1140067810
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1862474497
Short name T1
Test name
Test status
Simulation time 207806231126 ps
CPU time 159.25 seconds
Started Apr 25 12:42:43 PM PDT 24
Finished Apr 25 12:45:24 PM PDT 24
Peak memory 198164 kb
Host smart-149b2807-6319-4b43-b77a-34af66a87bd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862474497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1862474497
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3249429728
Short name T45
Test name
Test status
Simulation time 16771642 ps
CPU time 0.56 seconds
Started Apr 25 12:43:21 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 194632 kb
Host smart-2c578334-c8ad-4216-87fe-23eee05863d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249429728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3249429728
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3436745926
Short name T165
Test name
Test status
Simulation time 30911864 ps
CPU time 0.76 seconds
Started Apr 25 12:43:35 PM PDT 24
Finished Apr 25 12:43:37 PM PDT 24
Peak memory 195352 kb
Host smart-b3379f88-f018-4aaf-b38a-bd65a1136a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436745926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3436745926
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3399970024
Short name T674
Test name
Test status
Simulation time 312481807 ps
CPU time 15.97 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 198064 kb
Host smart-873a2d83-8582-4a76-a436-bc74dd9ee658
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399970024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3399970024
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2897795215
Short name T187
Test name
Test status
Simulation time 540278333 ps
CPU time 0.84 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:15 PM PDT 24
Peak memory 195900 kb
Host smart-931f5e6e-b393-45ad-84ba-6cf0f12d1a32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897795215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2897795215
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1096058954
Short name T698
Test name
Test status
Simulation time 119016277 ps
CPU time 1.02 seconds
Started Apr 25 12:43:29 PM PDT 24
Finished Apr 25 12:43:32 PM PDT 24
Peak memory 196160 kb
Host smart-e3093b84-4d8d-4c89-9e14-762b20b71d12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096058954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1096058954
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1959940923
Short name T716
Test name
Test status
Simulation time 73253376 ps
CPU time 3.02 seconds
Started Apr 25 12:43:25 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 198108 kb
Host smart-19243837-1987-4eb1-8dd2-8def221c2da7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959940923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1959940923
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1579646334
Short name T157
Test name
Test status
Simulation time 177336835 ps
CPU time 3.01 seconds
Started Apr 25 12:43:23 PM PDT 24
Finished Apr 25 12:43:27 PM PDT 24
Peak memory 197264 kb
Host smart-f283a4c3-c9f7-4c7b-a59e-166c64cde023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579646334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1579646334
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1972352542
Short name T411
Test name
Test status
Simulation time 284897006 ps
CPU time 1.14 seconds
Started Apr 25 12:43:22 PM PDT 24
Finished Apr 25 12:43:24 PM PDT 24
Peak memory 196580 kb
Host smart-825f37e6-8b80-4b6f-a417-415d2346082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972352542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1972352542
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.487839459
Short name T286
Test name
Test status
Simulation time 229833632 ps
CPU time 1.18 seconds
Started Apr 25 12:43:12 PM PDT 24
Finished Apr 25 12:43:18 PM PDT 24
Peak memory 196824 kb
Host smart-e92ba11b-99e1-453a-9680-2618cf580a09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487839459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.487839459
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1514079222
Short name T441
Test name
Test status
Simulation time 441362386 ps
CPU time 4.58 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:20 PM PDT 24
Peak memory 198000 kb
Host smart-c4fb9028-53f0-44a0-90cd-c024925e7975
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514079222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1514079222
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3913476133
Short name T527
Test name
Test status
Simulation time 136285984 ps
CPU time 1.08 seconds
Started Apr 25 12:43:14 PM PDT 24
Finished Apr 25 12:43:19 PM PDT 24
Peak memory 195608 kb
Host smart-4c25dd64-e484-4ad1-a742-0161e8dc4d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913476133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3913476133
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.4281961338
Short name T253
Test name
Test status
Simulation time 40800603 ps
CPU time 1.24 seconds
Started Apr 25 12:43:31 PM PDT 24
Finished Apr 25 12:43:34 PM PDT 24
Peak memory 196852 kb
Host smart-95f8fb96-af35-4345-b288-e182eeeda102
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281961338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.4281961338
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1420627765
Short name T551
Test name
Test status
Simulation time 26209698582 ps
CPU time 134.31 seconds
Started Apr 25 12:43:31 PM PDT 24
Finished Apr 25 12:45:47 PM PDT 24
Peak memory 198008 kb
Host smart-97e165f3-0272-4d1d-859b-0e5e52d192dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420627765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1420627765
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.1142452174
Short name T622
Test name
Test status
Simulation time 119851518783 ps
CPU time 635.11 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:54:13 PM PDT 24
Peak memory 198368 kb
Host smart-b45371d8-a1c5-4013-956a-a52ceb32c3a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1142452174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.1142452174
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2403491373
Short name T43
Test name
Test status
Simulation time 22064404 ps
CPU time 0.57 seconds
Started Apr 25 12:43:27 PM PDT 24
Finished Apr 25 12:43:29 PM PDT 24
Peak memory 194076 kb
Host smart-c9dbfe26-cae3-4c5a-bedc-c025c707d57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403491373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2403491373
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1473533303
Short name T226
Test name
Test status
Simulation time 112948993 ps
CPU time 0.87 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:31 PM PDT 24
Peak memory 196004 kb
Host smart-2c343ab6-6103-456a-9b70-5637a818bbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473533303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1473533303
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2118696604
Short name T506
Test name
Test status
Simulation time 146568787 ps
CPU time 7.12 seconds
Started Apr 25 12:43:12 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 197152 kb
Host smart-7ce685ed-c0cb-4ffb-820c-08ffcfa73390
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118696604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2118696604
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2270520796
Short name T145
Test name
Test status
Simulation time 29377156 ps
CPU time 0.68 seconds
Started Apr 25 12:43:20 PM PDT 24
Finished Apr 25 12:43:22 PM PDT 24
Peak memory 194636 kb
Host smart-a3c107d5-9cff-4ca4-aa87-2260c7ac8f8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270520796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2270520796
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.262621476
Short name T265
Test name
Test status
Simulation time 123109827 ps
CPU time 1.25 seconds
Started Apr 25 12:43:15 PM PDT 24
Finished Apr 25 12:43:19 PM PDT 24
Peak memory 197388 kb
Host smart-6beb29f2-8df8-4859-a523-f6f879cf0525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262621476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.262621476
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.302203647
Short name T390
Test name
Test status
Simulation time 61937794 ps
CPU time 2.51 seconds
Started Apr 25 12:43:25 PM PDT 24
Finished Apr 25 12:43:29 PM PDT 24
Peak memory 198128 kb
Host smart-81762188-b764-48ec-89aa-f3c70a68bc79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302203647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.302203647
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2674506332
Short name T628
Test name
Test status
Simulation time 1720814180 ps
CPU time 2 seconds
Started Apr 25 12:43:20 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 196216 kb
Host smart-f271267f-b08c-41d3-9128-6f6a5f9b462d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674506332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2674506332
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2200932686
Short name T616
Test name
Test status
Simulation time 32184596 ps
CPU time 1.01 seconds
Started Apr 25 12:43:14 PM PDT 24
Finished Apr 25 12:43:18 PM PDT 24
Peak memory 196012 kb
Host smart-056376e6-8f02-4a6e-a223-6558e6e415f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200932686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2200932686
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3086514463
Short name T369
Test name
Test status
Simulation time 144948164 ps
CPU time 1.03 seconds
Started Apr 25 12:43:14 PM PDT 24
Finished Apr 25 12:43:18 PM PDT 24
Peak memory 196552 kb
Host smart-2d98e8f5-8a2a-46be-91f4-61e839379d3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086514463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3086514463
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.238225724
Short name T79
Test name
Test status
Simulation time 147551899 ps
CPU time 1.48 seconds
Started Apr 25 12:43:20 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 198020 kb
Host smart-4948158e-9be1-45d5-8226-641ac847ded4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238225724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.238225724
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3867971122
Short name T397
Test name
Test status
Simulation time 189511359 ps
CPU time 0.96 seconds
Started Apr 25 12:43:19 PM PDT 24
Finished Apr 25 12:43:21 PM PDT 24
Peak memory 196552 kb
Host smart-ea132123-1562-4097-90bb-3a3c792dd949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867971122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3867971122
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3908601404
Short name T224
Test name
Test status
Simulation time 92536344 ps
CPU time 0.87 seconds
Started Apr 25 12:43:15 PM PDT 24
Finished Apr 25 12:43:19 PM PDT 24
Peak memory 196100 kb
Host smart-fbc8bc8c-0e04-4997-92d3-6b25b7cba198
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908601404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3908601404
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.625179422
Short name T442
Test name
Test status
Simulation time 13572398063 ps
CPU time 149.84 seconds
Started Apr 25 12:43:24 PM PDT 24
Finished Apr 25 12:45:55 PM PDT 24
Peak memory 198176 kb
Host smart-d99cad89-db75-4a5e-8a8b-c9d13f7d95f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625179422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.625179422
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2962331812
Short name T313
Test name
Test status
Simulation time 29151818 ps
CPU time 0.59 seconds
Started Apr 25 12:43:26 PM PDT 24
Finished Apr 25 12:43:28 PM PDT 24
Peak memory 194672 kb
Host smart-8dd58ce0-0e23-4a8e-84b4-763562c86929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962331812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2962331812
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2846566727
Short name T169
Test name
Test status
Simulation time 283468419 ps
CPU time 0.94 seconds
Started Apr 25 12:43:12 PM PDT 24
Finished Apr 25 12:43:17 PM PDT 24
Peak memory 195948 kb
Host smart-2d906b29-d3bb-47e6-9d4c-991b03e2b876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846566727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2846566727
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1572153047
Short name T220
Test name
Test status
Simulation time 1968503354 ps
CPU time 27.75 seconds
Started Apr 25 12:43:26 PM PDT 24
Finished Apr 25 12:43:55 PM PDT 24
Peak memory 197032 kb
Host smart-d35669e3-c94c-4b7e-82da-00af335c42d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572153047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1572153047
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.213311208
Short name T385
Test name
Test status
Simulation time 233434019 ps
CPU time 0.88 seconds
Started Apr 25 12:43:32 PM PDT 24
Finished Apr 25 12:43:34 PM PDT 24
Peak memory 196076 kb
Host smart-d82bf59d-a3dc-4aa4-a77f-af311c455e36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213311208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.213311208
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1901134198
Short name T444
Test name
Test status
Simulation time 146792376 ps
CPU time 1.28 seconds
Started Apr 25 12:43:32 PM PDT 24
Finished Apr 25 12:43:35 PM PDT 24
Peak memory 196896 kb
Host smart-bd377030-164e-4408-8e46-c6ae59b120b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901134198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1901134198
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1278317951
Short name T479
Test name
Test status
Simulation time 1112723467 ps
CPU time 3.19 seconds
Started Apr 25 12:43:16 PM PDT 24
Finished Apr 25 12:43:22 PM PDT 24
Peak memory 197116 kb
Host smart-a1225001-c600-440f-87fa-b4d87329f2f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278317951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1278317951
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3083978285
Short name T149
Test name
Test status
Simulation time 361408709 ps
CPU time 1.85 seconds
Started Apr 25 12:43:21 PM PDT 24
Finished Apr 25 12:43:24 PM PDT 24
Peak memory 195836 kb
Host smart-87457de0-70a2-4ab6-8915-963f4909393c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083978285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3083978285
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.9433240
Short name T524
Test name
Test status
Simulation time 241274376 ps
CPU time 1.16 seconds
Started Apr 25 12:43:22 PM PDT 24
Finished Apr 25 12:43:34 PM PDT 24
Peak memory 196968 kb
Host smart-730b99a0-ab7c-4200-87ac-24a9022cab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9433240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.9433240
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2662533671
Short name T722
Test name
Test status
Simulation time 56074119 ps
CPU time 1.08 seconds
Started Apr 25 12:43:14 PM PDT 24
Finished Apr 25 12:43:19 PM PDT 24
Peak memory 196048 kb
Host smart-16280fd5-ed3f-4738-873a-2749210c6a6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662533671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2662533671
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4083303538
Short name T418
Test name
Test status
Simulation time 136666919 ps
CPU time 2.41 seconds
Started Apr 25 12:43:23 PM PDT 24
Finished Apr 25 12:43:27 PM PDT 24
Peak memory 198076 kb
Host smart-c6c7eb7a-2ccf-4a17-81a7-805cde6b8ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083303538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.4083303538
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.155363695
Short name T281
Test name
Test status
Simulation time 148991125 ps
CPU time 0.87 seconds
Started Apr 25 12:43:17 PM PDT 24
Finished Apr 25 12:43:20 PM PDT 24
Peak memory 196512 kb
Host smart-c53bf2b8-676b-44ef-9026-3795b05c25d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155363695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.155363695
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.268644458
Short name T326
Test name
Test status
Simulation time 47026738 ps
CPU time 1.02 seconds
Started Apr 25 12:43:34 PM PDT 24
Finished Apr 25 12:43:37 PM PDT 24
Peak memory 196484 kb
Host smart-4719de27-9600-4b74-9cd7-b2d65ed55170
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268644458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.268644458
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3019886411
Short name T438
Test name
Test status
Simulation time 8495895210 ps
CPU time 92.8 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:45:11 PM PDT 24
Peak memory 198096 kb
Host smart-1ddf1676-2bb2-41de-be27-c51194d536bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019886411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3019886411
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1379909713
Short name T67
Test name
Test status
Simulation time 155261039822 ps
CPU time 987.68 seconds
Started Apr 25 12:43:31 PM PDT 24
Finished Apr 25 01:00:00 PM PDT 24
Peak memory 198312 kb
Host smart-fa56c198-c7c7-4009-8327-79e415e83f42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1379909713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1379909713
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1883238452
Short name T467
Test name
Test status
Simulation time 12439452 ps
CPU time 0.58 seconds
Started Apr 25 12:43:22 PM PDT 24
Finished Apr 25 12:43:25 PM PDT 24
Peak memory 194640 kb
Host smart-9c3dfab2-e038-4ca9-b813-ae03187f2eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883238452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1883238452
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1912589226
Short name T653
Test name
Test status
Simulation time 21337478 ps
CPU time 0.78 seconds
Started Apr 25 12:43:36 PM PDT 24
Finished Apr 25 12:43:38 PM PDT 24
Peak memory 196152 kb
Host smart-d93e44aa-c555-40e3-a2a5-fca483cd97f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912589226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1912589226
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2932846109
Short name T511
Test name
Test status
Simulation time 2345157274 ps
CPU time 11.78 seconds
Started Apr 25 12:43:33 PM PDT 24
Finished Apr 25 12:43:46 PM PDT 24
Peak memory 198124 kb
Host smart-e668c2b9-18a1-446c-a8db-0953ed276aa1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932846109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2932846109
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1138153559
Short name T484
Test name
Test status
Simulation time 234435636 ps
CPU time 0.88 seconds
Started Apr 25 12:43:29 PM PDT 24
Finished Apr 25 12:43:31 PM PDT 24
Peak memory 196840 kb
Host smart-da855407-24eb-4147-8fd1-e981b03b07e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138153559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1138153559
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.708031245
Short name T505
Test name
Test status
Simulation time 75646826 ps
CPU time 0.79 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:31 PM PDT 24
Peak memory 195484 kb
Host smart-1b050aa5-9bef-4bfd-85a0-2e3de7335d6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708031245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.708031245
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2458524632
Short name T426
Test name
Test status
Simulation time 275589950 ps
CPU time 2.64 seconds
Started Apr 25 12:43:34 PM PDT 24
Finished Apr 25 12:43:38 PM PDT 24
Peak memory 196332 kb
Host smart-1dbc1a21-c09a-4914-b9dd-eb0ace7f5069
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458524632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2458524632
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.974423363
Short name T319
Test name
Test status
Simulation time 123835060 ps
CPU time 1.98 seconds
Started Apr 25 12:43:46 PM PDT 24
Finished Apr 25 12:43:49 PM PDT 24
Peak memory 197112 kb
Host smart-246ac362-332b-4a8a-9f41-135d072bdf89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974423363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
974423363
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3876602189
Short name T305
Test name
Test status
Simulation time 30867675 ps
CPU time 0.72 seconds
Started Apr 25 12:43:29 PM PDT 24
Finished Apr 25 12:43:31 PM PDT 24
Peak memory 195100 kb
Host smart-f1e288fa-b5cc-4f2e-adbd-792eb0f06402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876602189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3876602189
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2782262333
Short name T521
Test name
Test status
Simulation time 35267181 ps
CPU time 0.99 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:41 PM PDT 24
Peak memory 195792 kb
Host smart-6e350ca0-c9de-42b4-b825-64e1ae9a9d2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782262333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2782262333
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3233412753
Short name T123
Test name
Test status
Simulation time 120593389 ps
CPU time 3.16 seconds
Started Apr 25 12:43:40 PM PDT 24
Finished Apr 25 12:43:45 PM PDT 24
Peak memory 198100 kb
Host smart-a71c0ba9-d2d7-4fa5-8952-baab86f4ea76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233412753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3233412753
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.478223267
Short name T75
Test name
Test status
Simulation time 80534529 ps
CPU time 0.79 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 195896 kb
Host smart-90c1b408-d120-41b9-86e0-0a32d9c11d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478223267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.478223267
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1401443177
Short name T608
Test name
Test status
Simulation time 157509112 ps
CPU time 1.15 seconds
Started Apr 25 12:43:24 PM PDT 24
Finished Apr 25 12:43:27 PM PDT 24
Peak memory 195500 kb
Host smart-abed48f0-fa5a-43e9-a348-def66fd3ed18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401443177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1401443177
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1318046984
Short name T354
Test name
Test status
Simulation time 40276673012 ps
CPU time 116.35 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:45:55 PM PDT 24
Peak memory 198228 kb
Host smart-8a729c5a-2989-4f9d-ac5f-d30889e3e870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318046984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1318046984
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.624873819
Short name T416
Test name
Test status
Simulation time 302708168447 ps
CPU time 1402 seconds
Started Apr 25 12:43:27 PM PDT 24
Finished Apr 25 01:06:51 PM PDT 24
Peak memory 198224 kb
Host smart-aabd14c6-bb19-4c65-a82f-e70b0d340605
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=624873819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.624873819
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.468011043
Short name T263
Test name
Test status
Simulation time 91891056 ps
CPU time 0.63 seconds
Started Apr 25 12:43:21 PM PDT 24
Finished Apr 25 12:43:23 PM PDT 24
Peak memory 194628 kb
Host smart-b73e0837-d92d-4570-a56e-d2ae4a076cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468011043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.468011043
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2370155593
Short name T223
Test name
Test status
Simulation time 76005666 ps
CPU time 0.76 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 195472 kb
Host smart-ef98d8bb-f8f7-4425-96ef-b1200b9f71e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370155593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2370155593
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.488580108
Short name T296
Test name
Test status
Simulation time 1123361466 ps
CPU time 25.91 seconds
Started Apr 25 12:43:26 PM PDT 24
Finished Apr 25 12:43:54 PM PDT 24
Peak memory 195468 kb
Host smart-8863973e-7628-4378-b7a8-3c7920c9da12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488580108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.488580108
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2123538021
Short name T211
Test name
Test status
Simulation time 144448373 ps
CPU time 0.64 seconds
Started Apr 25 12:43:30 PM PDT 24
Finished Apr 25 12:43:33 PM PDT 24
Peak memory 195376 kb
Host smart-2ee9d679-aade-4737-bdf3-05d781a27272
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123538021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2123538021
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.510288625
Short name T655
Test name
Test status
Simulation time 68202783 ps
CPU time 0.89 seconds
Started Apr 25 12:43:33 PM PDT 24
Finished Apr 25 12:43:35 PM PDT 24
Peak memory 196080 kb
Host smart-4805275d-dcc7-4809-9fdc-87621f528ba9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510288625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.510288625
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3446093402
Short name T606
Test name
Test status
Simulation time 281697825 ps
CPU time 2.53 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:32 PM PDT 24
Peak memory 196520 kb
Host smart-4c166ea2-4f5d-475e-989b-946c70f5c743
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446093402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3446093402
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3242786574
Short name T382
Test name
Test status
Simulation time 85452896 ps
CPU time 1.68 seconds
Started Apr 25 12:43:29 PM PDT 24
Finished Apr 25 12:43:36 PM PDT 24
Peak memory 195868 kb
Host smart-6ead3d79-3f49-4046-ba85-59057a6b4b09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242786574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3242786574
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4136134921
Short name T682
Test name
Test status
Simulation time 29186971 ps
CPU time 0.88 seconds
Started Apr 25 12:43:36 PM PDT 24
Finished Apr 25 12:43:38 PM PDT 24
Peak memory 197368 kb
Host smart-145c17da-72c4-4650-bd5a-806d108df988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136134921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4136134921
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.80052127
Short name T473
Test name
Test status
Simulation time 67969785 ps
CPU time 1.14 seconds
Started Apr 25 12:43:31 PM PDT 24
Finished Apr 25 12:43:36 PM PDT 24
Peak memory 196996 kb
Host smart-5ef551a1-0dc1-4fb2-9f68-c5963a062521
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80052127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup_
pulldown.80052127
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2353248283
Short name T394
Test name
Test status
Simulation time 931495167 ps
CPU time 3.85 seconds
Started Apr 25 12:43:44 PM PDT 24
Finished Apr 25 12:43:49 PM PDT 24
Peak memory 197992 kb
Host smart-4e932e30-1dec-47a3-80fe-8d36d6a2d164
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353248283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2353248283
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3390154625
Short name T13
Test name
Test status
Simulation time 56325997 ps
CPU time 1.09 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:31 PM PDT 24
Peak memory 196376 kb
Host smart-a9dd1ddb-9058-4887-88cc-ce49d650b212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390154625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3390154625
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.307516707
Short name T133
Test name
Test status
Simulation time 345079627 ps
CPU time 1.18 seconds
Started Apr 25 12:43:35 PM PDT 24
Finished Apr 25 12:43:37 PM PDT 24
Peak memory 195824 kb
Host smart-106a9da8-727e-45bc-8492-f983b91ec089
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307516707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.307516707
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1714783314
Short name T55
Test name
Test status
Simulation time 17472472481 ps
CPU time 146 seconds
Started Apr 25 12:43:27 PM PDT 24
Finished Apr 25 12:45:55 PM PDT 24
Peak memory 198292 kb
Host smart-a68a9d3d-458d-4f0b-acfa-ea93489f9849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714783314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1714783314
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3741575914
Short name T639
Test name
Test status
Simulation time 208829555008 ps
CPU time 2053.99 seconds
Started Apr 25 12:43:29 PM PDT 24
Finished Apr 25 01:17:45 PM PDT 24
Peak memory 198292 kb
Host smart-be338e71-87dd-40e5-8194-32ba9c236061
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3741575914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3741575914
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.625603542
Short name T218
Test name
Test status
Simulation time 95300182 ps
CPU time 0.57 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 194824 kb
Host smart-cfa7d9ca-3e1b-43d6-be09-41c10129f9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625603542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.625603542
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1342203080
Short name T156
Test name
Test status
Simulation time 72734973 ps
CPU time 0.71 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:39 PM PDT 24
Peak memory 195376 kb
Host smart-d7fbd504-428a-472f-a268-a3eeb8c0938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342203080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1342203080
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3786129478
Short name T439
Test name
Test status
Simulation time 9289915730 ps
CPU time 23.09 seconds
Started Apr 25 12:43:34 PM PDT 24
Finished Apr 25 12:43:58 PM PDT 24
Peak memory 196868 kb
Host smart-a4cc4f7b-2e40-491a-947f-bdba58f6fb48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786129478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3786129478
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.641053392
Short name T337
Test name
Test status
Simulation time 69618349 ps
CPU time 1.04 seconds
Started Apr 25 12:43:25 PM PDT 24
Finished Apr 25 12:43:28 PM PDT 24
Peak memory 197792 kb
Host smart-4d764d01-6705-4faa-86a7-535c86b941be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641053392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.641053392
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1497936980
Short name T339
Test name
Test status
Simulation time 50069394 ps
CPU time 1.31 seconds
Started Apr 25 12:43:26 PM PDT 24
Finished Apr 25 12:43:29 PM PDT 24
Peak memory 198112 kb
Host smart-ba0d1f57-9e35-4cfc-8859-dffbe1a0228b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497936980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1497936980
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3302619641
Short name T195
Test name
Test status
Simulation time 736898347 ps
CPU time 3.36 seconds
Started Apr 25 12:43:34 PM PDT 24
Finished Apr 25 12:43:39 PM PDT 24
Peak memory 198176 kb
Host smart-b30cd177-7bea-47dc-9a42-c6364d58cb05
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302619641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3302619641
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.899646193
Short name T687
Test name
Test status
Simulation time 514643094 ps
CPU time 2.74 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:42 PM PDT 24
Peak memory 197308 kb
Host smart-faa17c28-f5c4-44bf-9acb-4c0120a99c6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899646193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
899646193
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3442444332
Short name T535
Test name
Test status
Simulation time 55193551 ps
CPU time 1.1 seconds
Started Apr 25 12:43:27 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 195872 kb
Host smart-580e0b93-3a23-41d2-bbde-f22a6a22fad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442444332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3442444332
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3736359168
Short name T516
Test name
Test status
Simulation time 39483926 ps
CPU time 0.96 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 195640 kb
Host smart-8d44a101-7aa8-4650-bf7a-ac323125bc39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736359168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3736359168
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2164001751
Short name T366
Test name
Test status
Simulation time 670730923 ps
CPU time 3.74 seconds
Started Apr 25 12:43:30 PM PDT 24
Finished Apr 25 12:43:38 PM PDT 24
Peak memory 198048 kb
Host smart-0284a1ca-c945-4b74-8f9f-6ce3a6992730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164001751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2164001751
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2607336251
Short name T410
Test name
Test status
Simulation time 66062695 ps
CPU time 1.38 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:31 PM PDT 24
Peak memory 198000 kb
Host smart-bcd14545-4f3a-43ea-9ad7-a05b518f772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607336251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2607336251
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3482485202
Short name T456
Test name
Test status
Simulation time 85560877 ps
CPU time 0.84 seconds
Started Apr 25 12:43:36 PM PDT 24
Finished Apr 25 12:43:38 PM PDT 24
Peak memory 195192 kb
Host smart-1494ec55-ca0c-466d-bc81-a239c3cd15d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482485202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3482485202
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1579711973
Short name T571
Test name
Test status
Simulation time 45905604545 ps
CPU time 246.12 seconds
Started Apr 25 12:43:42 PM PDT 24
Finished Apr 25 12:47:50 PM PDT 24
Peak memory 198296 kb
Host smart-9df41670-a562-4175-be0d-911590a55bfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579711973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1579711973
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1946600561
Short name T68
Test name
Test status
Simulation time 326337560591 ps
CPU time 769.04 seconds
Started Apr 25 12:43:30 PM PDT 24
Finished Apr 25 12:56:24 PM PDT 24
Peak memory 198256 kb
Host smart-56fd7503-f2d3-4b1d-b1a1-8a3f9900987f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1946600561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1946600561
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1498584481
Short name T230
Test name
Test status
Simulation time 11972901 ps
CPU time 0.58 seconds
Started Apr 25 12:43:39 PM PDT 24
Finished Apr 25 12:43:41 PM PDT 24
Peak memory 193932 kb
Host smart-3c680412-65ff-4a97-b314-df9d19f18efa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498584481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1498584481
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.4049123084
Short name T172
Test name
Test status
Simulation time 47931435 ps
CPU time 0.91 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 197324 kb
Host smart-5ba37341-9402-4146-bf84-75c6316aee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049123084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.4049123084
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3121908809
Short name T221
Test name
Test status
Simulation time 201997148 ps
CPU time 9.68 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:48 PM PDT 24
Peak memory 195532 kb
Host smart-c4cea132-3b14-4dae-a478-a3ff0155c15a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121908809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3121908809
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1000731678
Short name T631
Test name
Test status
Simulation time 587757157 ps
CPU time 0.99 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 196684 kb
Host smart-35017e05-2514-42aa-a8eb-688c64988fad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000731678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1000731678
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3485715562
Short name T714
Test name
Test status
Simulation time 51970256 ps
CPU time 1 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:30 PM PDT 24
Peak memory 196816 kb
Host smart-f1e72bfd-5711-4977-8918-eeba7911687e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485715562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3485715562
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1870858928
Short name T381
Test name
Test status
Simulation time 247140369 ps
CPU time 1.29 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:41 PM PDT 24
Peak memory 198032 kb
Host smart-c6001c6e-61ef-4757-99c1-373ac530e129
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870858928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1870858928
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3432246973
Short name T530
Test name
Test status
Simulation time 74950128 ps
CPU time 1.09 seconds
Started Apr 25 12:43:29 PM PDT 24
Finished Apr 25 12:43:32 PM PDT 24
Peak memory 195624 kb
Host smart-ebc677a8-5a5a-4208-9cd2-7f54d27c8d03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432246973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3432246973
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.873561813
Short name T132
Test name
Test status
Simulation time 53382464 ps
CPU time 0.83 seconds
Started Apr 25 12:43:41 PM PDT 24
Finished Apr 25 12:43:43 PM PDT 24
Peak memory 196716 kb
Host smart-22e32953-1d5b-41c8-8437-07453c7945e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873561813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.873561813
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1607170214
Short name T241
Test name
Test status
Simulation time 32898621 ps
CPU time 0.85 seconds
Started Apr 25 12:43:39 PM PDT 24
Finished Apr 25 12:43:42 PM PDT 24
Peak memory 195972 kb
Host smart-ef7be09a-c3e7-4757-ac1b-e4b5823d792c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607170214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1607170214
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1322386473
Short name T693
Test name
Test status
Simulation time 207935517 ps
CPU time 3.59 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:43 PM PDT 24
Peak memory 198024 kb
Host smart-23b30ab2-d6c5-42cf-81bb-933862bb3d61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322386473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1322386473
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1111374706
Short name T222
Test name
Test status
Simulation time 33669831 ps
CPU time 0.96 seconds
Started Apr 25 12:43:29 PM PDT 24
Finished Apr 25 12:43:32 PM PDT 24
Peak memory 196564 kb
Host smart-1936d0ad-6abb-4421-8f28-74b6e78c84d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111374706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1111374706
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1043814178
Short name T202
Test name
Test status
Simulation time 36786641 ps
CPU time 0.82 seconds
Started Apr 25 12:43:42 PM PDT 24
Finished Apr 25 12:43:44 PM PDT 24
Peak memory 195416 kb
Host smart-b31fc38e-3782-4d37-af30-40070cc9ccf7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043814178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1043814178
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.739449368
Short name T686
Test name
Test status
Simulation time 20258660265 ps
CPU time 128.5 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:45:47 PM PDT 24
Peak memory 198196 kb
Host smart-cf0a603a-0841-4892-b518-59c5bd22aa5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739449368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.739449368
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3649868051
Short name T554
Test name
Test status
Simulation time 74226696388 ps
CPU time 819.97 seconds
Started Apr 25 12:43:35 PM PDT 24
Finished Apr 25 12:57:16 PM PDT 24
Peak memory 198188 kb
Host smart-f7793ca4-30c7-413a-a24c-66824a389d1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3649868051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3649868051
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3085425655
Short name T249
Test name
Test status
Simulation time 13576704 ps
CPU time 0.56 seconds
Started Apr 25 12:44:01 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 193932 kb
Host smart-e3f689ef-6aeb-4320-a02e-2a602ca41ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085425655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3085425655
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2186002652
Short name T375
Test name
Test status
Simulation time 121573816 ps
CPU time 0.78 seconds
Started Apr 25 12:43:35 PM PDT 24
Finished Apr 25 12:43:37 PM PDT 24
Peak memory 195304 kb
Host smart-47c87b92-8dae-42f4-987b-617713f25955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186002652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2186002652
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1435392613
Short name T297
Test name
Test status
Simulation time 1826075401 ps
CPU time 24.06 seconds
Started Apr 25 12:43:28 PM PDT 24
Finished Apr 25 12:43:54 PM PDT 24
Peak memory 195596 kb
Host smart-eb5f58e8-58b2-4e6d-810e-ae68d3b448a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435392613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1435392613
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3373808111
Short name T342
Test name
Test status
Simulation time 63703808 ps
CPU time 1 seconds
Started Apr 25 12:43:35 PM PDT 24
Finished Apr 25 12:43:37 PM PDT 24
Peak memory 196552 kb
Host smart-1ff6fb63-70c9-4a82-867c-f13805b7196b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373808111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3373808111
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.4120888862
Short name T515
Test name
Test status
Simulation time 192345434 ps
CPU time 1.04 seconds
Started Apr 25 12:43:39 PM PDT 24
Finished Apr 25 12:43:42 PM PDT 24
Peak memory 196688 kb
Host smart-90592541-59ba-4b24-ac03-65173c71b0ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120888862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.4120888862
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1917904075
Short name T140
Test name
Test status
Simulation time 48111521 ps
CPU time 1.16 seconds
Started Apr 25 12:43:29 PM PDT 24
Finished Apr 25 12:43:32 PM PDT 24
Peak memory 196712 kb
Host smart-b734263a-8870-4ee9-b349-8feae0268a3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917904075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1917904075
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.224728653
Short name T173
Test name
Test status
Simulation time 383524383 ps
CPU time 1.54 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:39 PM PDT 24
Peak memory 196584 kb
Host smart-98d687f8-43a1-4c92-936b-c77f19719c2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224728653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
224728653
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1783439858
Short name T547
Test name
Test status
Simulation time 94079457 ps
CPU time 0.96 seconds
Started Apr 25 12:43:35 PM PDT 24
Finished Apr 25 12:43:37 PM PDT 24
Peak memory 195872 kb
Host smart-6814662d-523a-4c8d-a3a8-f41aa38a888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783439858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1783439858
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2758722154
Short name T504
Test name
Test status
Simulation time 68707378 ps
CPU time 0.89 seconds
Started Apr 25 12:43:34 PM PDT 24
Finished Apr 25 12:43:35 PM PDT 24
Peak memory 196720 kb
Host smart-0f42d57c-5c45-4909-b32d-79db271a2a5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758722154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2758722154
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1448526308
Short name T374
Test name
Test status
Simulation time 579160253 ps
CPU time 2.03 seconds
Started Apr 25 12:43:25 PM PDT 24
Finished Apr 25 12:43:28 PM PDT 24
Peak memory 197992 kb
Host smart-ca1ccf12-16b4-421e-9fe3-06f934583e15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448526308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1448526308
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2754125399
Short name T274
Test name
Test status
Simulation time 193333699 ps
CPU time 0.76 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:38 PM PDT 24
Peak memory 195452 kb
Host smart-3c420d9b-4250-4cac-a076-378a3ae266ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754125399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2754125399
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4264071179
Short name T365
Test name
Test status
Simulation time 39293518 ps
CPU time 1.16 seconds
Started Apr 25 12:43:26 PM PDT 24
Finished Apr 25 12:43:28 PM PDT 24
Peak memory 195868 kb
Host smart-d96f93b6-2f0b-48e4-a7a1-a4ddcc71a899
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264071179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4264071179
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.118467998
Short name T610
Test name
Test status
Simulation time 13550605150 ps
CPU time 48.28 seconds
Started Apr 25 12:43:41 PM PDT 24
Finished Apr 25 12:44:31 PM PDT 24
Peak memory 198172 kb
Host smart-bdf059e0-a3cc-4573-a1ee-6fb2663a9d4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118467998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.118467998
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3852143189
Short name T166
Test name
Test status
Simulation time 25791770 ps
CPU time 0.58 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 194000 kb
Host smart-1cd1673f-afa7-4d3d-ac7a-21947ae6b9b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852143189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3852143189
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3938949397
Short name T419
Test name
Test status
Simulation time 33180297 ps
CPU time 0.78 seconds
Started Apr 25 12:43:40 PM PDT 24
Finished Apr 25 12:43:43 PM PDT 24
Peak memory 196096 kb
Host smart-a3758bc9-ca14-4bd8-aa84-fc57698b58a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938949397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3938949397
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.142614033
Short name T546
Test name
Test status
Simulation time 593274177 ps
CPU time 17.47 seconds
Started Apr 25 12:43:44 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 196788 kb
Host smart-a73840e1-3538-4cc0-a371-e279ade22f0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142614033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.142614033
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.4181604557
Short name T619
Test name
Test status
Simulation time 81318951 ps
CPU time 0.99 seconds
Started Apr 25 12:43:43 PM PDT 24
Finished Apr 25 12:43:46 PM PDT 24
Peak memory 196704 kb
Host smart-697cbeb2-9dcc-42a2-b5fc-7083471eefd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181604557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4181604557
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2285000711
Short name T314
Test name
Test status
Simulation time 607233425 ps
CPU time 1.39 seconds
Started Apr 25 12:43:42 PM PDT 24
Finished Apr 25 12:43:45 PM PDT 24
Peak memory 197060 kb
Host smart-1eb1d13f-5423-4ab2-b127-50dcf6d68fb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285000711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2285000711
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3598164567
Short name T254
Test name
Test status
Simulation time 71361888 ps
CPU time 2.64 seconds
Started Apr 25 12:43:39 PM PDT 24
Finished Apr 25 12:43:43 PM PDT 24
Peak memory 198060 kb
Host smart-f8f5d911-3e35-454e-879d-3b1e267ec157
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598164567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3598164567
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3905280622
Short name T152
Test name
Test status
Simulation time 382826460 ps
CPU time 1.97 seconds
Started Apr 25 12:43:40 PM PDT 24
Finished Apr 25 12:43:44 PM PDT 24
Peak memory 195784 kb
Host smart-fa8e9c96-2958-4a18-bb81-83e0eb3ccf1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905280622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3905280622
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2205190407
Short name T125
Test name
Test status
Simulation time 54743597 ps
CPU time 0.65 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 195352 kb
Host smart-d6ee89f8-5821-45c0-8566-44bdcb044342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205190407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2205190407
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3768852143
Short name T432
Test name
Test status
Simulation time 112430891 ps
CPU time 1.16 seconds
Started Apr 25 12:43:41 PM PDT 24
Finished Apr 25 12:43:43 PM PDT 24
Peak memory 197112 kb
Host smart-6fae20e1-824c-4900-a271-79ad91df355b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768852143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3768852143
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.4013703615
Short name T212
Test name
Test status
Simulation time 41314931 ps
CPU time 1.87 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:41 PM PDT 24
Peak memory 198024 kb
Host smart-5e3e8f50-bb06-4fbf-8de4-951d2ddf10ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013703615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.4013703615
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.612435695
Short name T39
Test name
Test status
Simulation time 38692976 ps
CPU time 0.88 seconds
Started Apr 25 12:43:35 PM PDT 24
Finished Apr 25 12:43:37 PM PDT 24
Peak memory 196000 kb
Host smart-e00e5481-5fba-45f1-a145-814d1734d3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612435695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.612435695
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.658882231
Short name T174
Test name
Test status
Simulation time 89918647 ps
CPU time 1.05 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:39 PM PDT 24
Peak memory 195592 kb
Host smart-4004f0a9-2fdd-4247-b284-01b1c03840b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658882231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.658882231
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2857760769
Short name T9
Test name
Test status
Simulation time 80255388682 ps
CPU time 213.92 seconds
Started Apr 25 12:43:45 PM PDT 24
Finished Apr 25 12:47:21 PM PDT 24
Peak memory 198124 kb
Host smart-febe9f43-8d69-4056-8b2f-40a8dc683242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857760769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2857760769
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.4291379604
Short name T34
Test name
Test status
Simulation time 37145938949 ps
CPU time 561.07 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 12:53:17 PM PDT 24
Peak memory 198312 kb
Host smart-6727a6df-83f8-4893-9ebb-9dae632b5eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4291379604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.4291379604
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3040910801
Short name T359
Test name
Test status
Simulation time 17584600 ps
CPU time 0.59 seconds
Started Apr 25 12:43:38 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 194196 kb
Host smart-4c9bfae0-ebc9-4118-b52d-7554d3c292f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040910801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3040910801
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.637506174
Short name T711
Test name
Test status
Simulation time 45076790 ps
CPU time 0.68 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 194176 kb
Host smart-b700743e-c293-4e3a-9211-a9cf45455528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637506174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.637506174
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3434422487
Short name T273
Test name
Test status
Simulation time 3245069033 ps
CPU time 27.54 seconds
Started Apr 25 12:43:40 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 196728 kb
Host smart-2be57d25-59c1-4926-8765-0638943b753a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434422487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3434422487
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.379763162
Short name T392
Test name
Test status
Simulation time 63950466 ps
CPU time 0.9 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 197076 kb
Host smart-e9b8b00e-9adb-4704-aed2-4f3b25477b5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379763162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.379763162
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.221816396
Short name T508
Test name
Test status
Simulation time 241035055 ps
CPU time 1.18 seconds
Started Apr 25 12:43:41 PM PDT 24
Finished Apr 25 12:43:44 PM PDT 24
Peak memory 196644 kb
Host smart-cf8fbae6-f788-4756-a2bd-d886dc8a5780
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221816396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.221816396
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2242345713
Short name T590
Test name
Test status
Simulation time 32172846 ps
CPU time 1.32 seconds
Started Apr 25 12:43:50 PM PDT 24
Finished Apr 25 12:43:52 PM PDT 24
Peak memory 196544 kb
Host smart-7dc708c8-a41d-48dc-8aac-c11457336dc3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242345713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2242345713
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2576941244
Short name T301
Test name
Test status
Simulation time 478998277 ps
CPU time 1.81 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:01 PM PDT 24
Peak memory 195848 kb
Host smart-42c41dd0-e370-4f2b-bf67-a783dbe29551
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576941244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2576941244
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1395561313
Short name T74
Test name
Test status
Simulation time 346314354 ps
CPU time 1.05 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:43:58 PM PDT 24
Peak memory 196016 kb
Host smart-81f7fad8-cb74-4ae9-a108-6d102a08f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395561313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1395561313
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.307298492
Short name T671
Test name
Test status
Simulation time 625316176 ps
CPU time 1.31 seconds
Started Apr 25 12:43:47 PM PDT 24
Finished Apr 25 12:43:49 PM PDT 24
Peak memory 197092 kb
Host smart-a89366cf-3e4f-426d-a2d0-1fad6aa42479
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307298492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.307298492
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3700203120
Short name T328
Test name
Test status
Simulation time 273480266 ps
CPU time 2.85 seconds
Started Apr 25 12:43:49 PM PDT 24
Finished Apr 25 12:43:53 PM PDT 24
Peak memory 197968 kb
Host smart-bef07110-d668-48d3-8177-e388311bbf0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700203120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3700203120
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1383304947
Short name T242
Test name
Test status
Simulation time 105637946 ps
CPU time 1.51 seconds
Started Apr 25 12:44:01 PM PDT 24
Finished Apr 25 12:44:04 PM PDT 24
Peak memory 195592 kb
Host smart-62841f99-f107-4527-8490-8fe3703fc1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383304947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1383304947
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1539121061
Short name T243
Test name
Test status
Simulation time 29863801 ps
CPU time 0.93 seconds
Started Apr 25 12:43:44 PM PDT 24
Finished Apr 25 12:43:47 PM PDT 24
Peak memory 196560 kb
Host smart-92457879-e039-4e34-b39e-115091962499
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539121061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1539121061
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.929489850
Short name T496
Test name
Test status
Simulation time 5530857804 ps
CPU time 74.72 seconds
Started Apr 25 12:44:19 PM PDT 24
Finished Apr 25 12:45:37 PM PDT 24
Peak memory 198132 kb
Host smart-df10f235-0484-4cd1-919b-3f3f4a6dd769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929489850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.929489850
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.4021443040
Short name T582
Test name
Test status
Simulation time 9887799385 ps
CPU time 318.7 seconds
Started Apr 25 12:43:45 PM PDT 24
Finished Apr 25 12:49:05 PM PDT 24
Peak memory 198312 kb
Host smart-b2865114-e346-4769-92a2-759f42a765c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4021443040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.4021443040
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1412396487
Short name T324
Test name
Test status
Simulation time 38271714 ps
CPU time 0.57 seconds
Started Apr 25 12:42:48 PM PDT 24
Finished Apr 25 12:42:51 PM PDT 24
Peak memory 194580 kb
Host smart-f639c11e-9734-4a39-8efb-30d6b2ef2007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412396487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1412396487
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2845869627
Short name T50
Test name
Test status
Simulation time 34337938 ps
CPU time 0.74 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:50 PM PDT 24
Peak memory 194220 kb
Host smart-2026dc4d-3af7-4dad-bb0a-5bb2a4099e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845869627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2845869627
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.568124756
Short name T147
Test name
Test status
Simulation time 272628539 ps
CPU time 13.54 seconds
Started Apr 25 12:42:45 PM PDT 24
Finished Apr 25 12:43:00 PM PDT 24
Peak memory 196840 kb
Host smart-81c68158-430f-4454-a746-fc2dd4d23038
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568124756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.568124756
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2550892115
Short name T44
Test name
Test status
Simulation time 245348013 ps
CPU time 1.11 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:50 PM PDT 24
Peak memory 196700 kb
Host smart-8e6c5baf-cc5e-463d-8e5d-c70b30ef4d8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550892115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2550892115
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1518978270
Short name T498
Test name
Test status
Simulation time 23397598 ps
CPU time 0.7 seconds
Started Apr 25 12:42:45 PM PDT 24
Finished Apr 25 12:42:47 PM PDT 24
Peak memory 194440 kb
Host smart-04df0493-256c-49f5-beca-a742d729bb11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518978270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1518978270
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2591834467
Short name T282
Test name
Test status
Simulation time 145330405 ps
CPU time 3.02 seconds
Started Apr 25 12:42:44 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 198032 kb
Host smart-1cd8f704-a15e-41e7-9669-8c8c4a195544
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591834467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2591834467
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.518755080
Short name T563
Test name
Test status
Simulation time 64709720 ps
CPU time 1.58 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:51 PM PDT 24
Peak memory 195964 kb
Host smart-03e40ac0-694f-48e7-9c1e-27c279df59ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518755080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.518755080
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1966984069
Short name T260
Test name
Test status
Simulation time 123341200 ps
CPU time 1.15 seconds
Started Apr 25 12:42:44 PM PDT 24
Finished Apr 25 12:42:46 PM PDT 24
Peak memory 196040 kb
Host smart-da40676e-51af-46b1-b28b-7621389c4dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966984069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1966984069
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1742204953
Short name T595
Test name
Test status
Simulation time 133694166 ps
CPU time 1.1 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:51 PM PDT 24
Peak memory 195864 kb
Host smart-7b18aa53-5057-412c-b909-afb076746125
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742204953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1742204953
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.158364996
Short name T16
Test name
Test status
Simulation time 73245208 ps
CPU time 3.2 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:52 PM PDT 24
Peak memory 197976 kb
Host smart-6923c455-ea91-4ff8-9ab4-70705075fa5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158364996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.158364996
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3389183298
Short name T41
Test name
Test status
Simulation time 66039550 ps
CPU time 0.85 seconds
Started Apr 25 12:42:46 PM PDT 24
Finished Apr 25 12:42:49 PM PDT 24
Peak memory 213892 kb
Host smart-302f1c7b-e358-4492-84b0-201f33f7ca5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389183298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3389183298
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1682887046
Short name T573
Test name
Test status
Simulation time 338130552 ps
CPU time 1.39 seconds
Started Apr 25 12:42:48 PM PDT 24
Finished Apr 25 12:42:52 PM PDT 24
Peak memory 195544 kb
Host smart-05f260f9-2642-4a36-9cf3-f3460cef6432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682887046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1682887046
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1214780846
Short name T528
Test name
Test status
Simulation time 188226883 ps
CPU time 1.5 seconds
Started Apr 25 12:42:47 PM PDT 24
Finished Apr 25 12:42:51 PM PDT 24
Peak memory 195628 kb
Host smart-2138770f-eca4-40b8-9baa-2268ff806835
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214780846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1214780846
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3156683103
Short name T344
Test name
Test status
Simulation time 25291978409 ps
CPU time 84.13 seconds
Started Apr 25 12:42:46 PM PDT 24
Finished Apr 25 12:44:12 PM PDT 24
Peak memory 198272 kb
Host smart-b12f007c-3ffb-44f7-8a89-6b328dc8feae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156683103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3156683103
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.527494102
Short name T316
Test name
Test status
Simulation time 65418757274 ps
CPU time 544.69 seconds
Started Apr 25 12:42:46 PM PDT 24
Finished Apr 25 12:51:53 PM PDT 24
Peak memory 198260 kb
Host smart-e3d6a23e-24fd-4412-9e40-b25803e26cb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=527494102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.527494102
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.4051992035
Short name T523
Test name
Test status
Simulation time 86470807 ps
CPU time 0.9 seconds
Started Apr 25 12:43:42 PM PDT 24
Finished Apr 25 12:43:45 PM PDT 24
Peak memory 196588 kb
Host smart-655f5b70-b7a0-4266-af87-097ec9e6228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051992035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.4051992035
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.483162214
Short name T549
Test name
Test status
Simulation time 662476925 ps
CPU time 11.93 seconds
Started Apr 25 12:43:52 PM PDT 24
Finished Apr 25 12:44:05 PM PDT 24
Peak memory 197996 kb
Host smart-1ca9c09f-cc26-4049-a25b-25641a2ba14a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483162214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.483162214
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1088888452
Short name T329
Test name
Test status
Simulation time 68351550 ps
CPU time 0.98 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 12:43:56 PM PDT 24
Peak memory 196600 kb
Host smart-6cf2f503-f5aa-4b34-9bb4-a2e4628847b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088888452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1088888452
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2007701463
Short name T478
Test name
Test status
Simulation time 60033553 ps
CPU time 1.18 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 195912 kb
Host smart-1a890797-bb21-4a22-9835-370f36f292c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007701463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2007701463
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.120904289
Short name T175
Test name
Test status
Simulation time 86886211 ps
CPU time 2.9 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:05 PM PDT 24
Peak memory 198012 kb
Host smart-d8eb985f-39aa-4b36-8670-3ce88d4a18ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120904289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.120904289
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2435248490
Short name T702
Test name
Test status
Simulation time 356244622 ps
CPU time 1.22 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 195736 kb
Host smart-a23e91c3-9393-40db-af73-2e466b76431b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435248490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2435248490
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3440264759
Short name T28
Test name
Test status
Simulation time 35565381 ps
CPU time 1.27 seconds
Started Apr 25 12:43:53 PM PDT 24
Finished Apr 25 12:43:55 PM PDT 24
Peak memory 197040 kb
Host smart-a165519a-b074-4f4e-b78e-9510c36ddacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440264759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3440264759
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.555280295
Short name T122
Test name
Test status
Simulation time 46083288 ps
CPU time 0.88 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 12:43:56 PM PDT 24
Peak memory 196000 kb
Host smart-4e4adc16-4454-4056-be84-266cf926ee74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555280295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.555280295
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3870432871
Short name T389
Test name
Test status
Simulation time 258471923 ps
CPU time 3.09 seconds
Started Apr 25 12:43:51 PM PDT 24
Finished Apr 25 12:43:55 PM PDT 24
Peak memory 197984 kb
Host smart-af85524b-2b34-43a0-9ef5-4e371c09c99a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870432871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3870432871
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3436796570
Short name T550
Test name
Test status
Simulation time 343036691 ps
CPU time 1.17 seconds
Started Apr 25 12:43:37 PM PDT 24
Finished Apr 25 12:43:40 PM PDT 24
Peak memory 196584 kb
Host smart-eb2b0a97-2527-4443-a17a-8fc55373a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436796570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3436796570
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.902548833
Short name T27
Test name
Test status
Simulation time 56500546 ps
CPU time 1.39 seconds
Started Apr 25 12:43:36 PM PDT 24
Finished Apr 25 12:43:38 PM PDT 24
Peak memory 195580 kb
Host smart-31b8e7b7-6874-4b42-bcc4-81cb593d1142
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902548833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.902548833
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2665183831
Short name T623
Test name
Test status
Simulation time 24639881033 ps
CPU time 174.84 seconds
Started Apr 25 12:44:10 PM PDT 24
Finished Apr 25 12:47:09 PM PDT 24
Peak memory 198180 kb
Host smart-44c8e671-e39e-4747-b37e-0b0afcc38fa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665183831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2665183831
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.782116672
Short name T300
Test name
Test status
Simulation time 123860656475 ps
CPU time 1442.35 seconds
Started Apr 25 12:43:44 PM PDT 24
Finished Apr 25 01:07:49 PM PDT 24
Peak memory 198284 kb
Host smart-fa8977d1-977b-42fe-9142-dd83d7eda71d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=782116672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.782116672
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3504956031
Short name T348
Test name
Test status
Simulation time 14563641 ps
CPU time 0.59 seconds
Started Apr 25 12:43:56 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 194664 kb
Host smart-c64d72bf-dd7a-47d3-93ae-157c32a0f605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504956031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3504956031
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1173063874
Short name T514
Test name
Test status
Simulation time 45376903 ps
CPU time 0.9 seconds
Started Apr 25 12:43:43 PM PDT 24
Finished Apr 25 12:43:45 PM PDT 24
Peak memory 196644 kb
Host smart-b5a78019-b598-43f4-953c-31f1b5c8fb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173063874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1173063874
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1414023590
Short name T262
Test name
Test status
Simulation time 1586453939 ps
CPU time 25.94 seconds
Started Apr 25 12:43:52 PM PDT 24
Finished Apr 25 12:44:19 PM PDT 24
Peak memory 197972 kb
Host smart-d22b7911-bec4-4d84-a01b-f143126fcdad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414023590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1414023590
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.237281128
Short name T576
Test name
Test status
Simulation time 111288168 ps
CPU time 0.89 seconds
Started Apr 25 12:43:41 PM PDT 24
Finished Apr 25 12:43:44 PM PDT 24
Peak memory 197832 kb
Host smart-fb270860-1bf3-47fc-b3cf-b281fcf0c08e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237281128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.237281128
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.287236480
Short name T256
Test name
Test status
Simulation time 54310931 ps
CPU time 1.4 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 12:43:57 PM PDT 24
Peak memory 195900 kb
Host smart-c25bdd42-97f9-4adb-89c6-a84b868b7ab6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287236480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.287236480
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3052347762
Short name T534
Test name
Test status
Simulation time 167337710 ps
CPU time 1.74 seconds
Started Apr 25 12:44:13 PM PDT 24
Finished Apr 25 12:44:18 PM PDT 24
Peak memory 198108 kb
Host smart-49256107-619b-49a1-82e8-90736b0021a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052347762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3052347762
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.83511943
Short name T694
Test name
Test status
Simulation time 1287674250 ps
CPU time 2.71 seconds
Started Apr 25 12:43:46 PM PDT 24
Finished Apr 25 12:43:50 PM PDT 24
Peak memory 198020 kb
Host smart-f22e465d-1512-46fa-9558-7e85239e55fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83511943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.83511943
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2905123902
Short name T372
Test name
Test status
Simulation time 192733107 ps
CPU time 1.23 seconds
Started Apr 25 12:44:03 PM PDT 24
Finished Apr 25 12:44:05 PM PDT 24
Peak memory 196516 kb
Host smart-ae2f5028-f46c-48f9-b233-f69eb9552115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905123902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2905123902
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1047360156
Short name T238
Test name
Test status
Simulation time 206467270 ps
CPU time 1.21 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:00 PM PDT 24
Peak memory 197308 kb
Host smart-39a372bc-aa38-44e6-bdcc-c152f0bbaffa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047360156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1047360156
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2708956646
Short name T311
Test name
Test status
Simulation time 247859606 ps
CPU time 1.35 seconds
Started Apr 25 12:43:49 PM PDT 24
Finished Apr 25 12:43:51 PM PDT 24
Peak memory 198008 kb
Host smart-008d95bf-5ddc-4a2b-9a65-c63d0d8dbf30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708956646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2708956646
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3970224422
Short name T259
Test name
Test status
Simulation time 139659576 ps
CPU time 0.84 seconds
Started Apr 25 12:43:43 PM PDT 24
Finished Apr 25 12:43:46 PM PDT 24
Peak memory 195292 kb
Host smart-04c681e2-ffbc-4f52-b435-de8dd9c3363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970224422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3970224422
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1989731890
Short name T542
Test name
Test status
Simulation time 175778006 ps
CPU time 1.14 seconds
Started Apr 25 12:43:53 PM PDT 24
Finished Apr 25 12:43:56 PM PDT 24
Peak memory 195856 kb
Host smart-51ddab8e-14c0-4e9a-aed3-58a0511bddc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989731890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1989731890
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3231125766
Short name T513
Test name
Test status
Simulation time 3920748658 ps
CPU time 47.55 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:44:45 PM PDT 24
Peak memory 198136 kb
Host smart-03f18948-3ca7-40c6-bcf9-04290a85a43a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231125766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3231125766
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.327179461
Short name T289
Test name
Test status
Simulation time 24265816 ps
CPU time 0.57 seconds
Started Apr 25 12:43:46 PM PDT 24
Finished Apr 25 12:43:48 PM PDT 24
Peak memory 193956 kb
Host smart-96f2e37d-c0e8-4489-9c4d-e92ad951240a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327179461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.327179461
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2738100263
Short name T612
Test name
Test status
Simulation time 125605859 ps
CPU time 0.81 seconds
Started Apr 25 12:43:49 PM PDT 24
Finished Apr 25 12:43:50 PM PDT 24
Peak memory 196088 kb
Host smart-326e38a0-8b2d-4312-b1f5-4317c9ad3a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738100263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2738100263
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3036613265
Short name T233
Test name
Test status
Simulation time 3564479589 ps
CPU time 24.72 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:24 PM PDT 24
Peak memory 196936 kb
Host smart-62683cd5-bd11-4829-8987-66b7a959b845
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036613265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3036613265
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1932694337
Short name T570
Test name
Test status
Simulation time 30889122 ps
CPU time 0.67 seconds
Started Apr 25 12:43:42 PM PDT 24
Finished Apr 25 12:43:44 PM PDT 24
Peak memory 194620 kb
Host smart-6fd892e3-de53-4d08-b621-dd64ff10fb46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932694337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1932694337
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3146665785
Short name T231
Test name
Test status
Simulation time 244743630 ps
CPU time 1.17 seconds
Started Apr 25 12:43:42 PM PDT 24
Finished Apr 25 12:43:44 PM PDT 24
Peak memory 196584 kb
Host smart-d49c72f7-8a8d-4089-8ad4-1ea6fab4d4c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146665785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3146665785
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.164719656
Short name T401
Test name
Test status
Simulation time 66885403 ps
CPU time 2.42 seconds
Started Apr 25 12:43:53 PM PDT 24
Finished Apr 25 12:43:57 PM PDT 24
Peak memory 198060 kb
Host smart-ef5eb9ef-6444-4c5f-8946-9a093cdcfe98
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164719656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.164719656
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2327834429
Short name T129
Test name
Test status
Simulation time 1045967312 ps
CPU time 2.66 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:08 PM PDT 24
Peak memory 197348 kb
Host smart-e385458b-48f4-4015-bab6-392c09ca82b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327834429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2327834429
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.4269987214
Short name T367
Test name
Test status
Simulation time 47121032 ps
CPU time 0.99 seconds
Started Apr 25 12:43:43 PM PDT 24
Finished Apr 25 12:43:46 PM PDT 24
Peak memory 195884 kb
Host smart-528387fe-d916-4ef9-bb9b-db033b87555b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269987214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.4269987214
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2350053848
Short name T618
Test name
Test status
Simulation time 144175066 ps
CPU time 1.36 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:07 PM PDT 24
Peak memory 198112 kb
Host smart-39b2a53d-0fe2-45fb-a669-f144fc8f4e3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350053848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2350053848
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1576190295
Short name T569
Test name
Test status
Simulation time 193156367 ps
CPU time 2.27 seconds
Started Apr 25 12:43:40 PM PDT 24
Finished Apr 25 12:43:44 PM PDT 24
Peak memory 197952 kb
Host smart-96084d5c-8021-4fe8-9b20-291975250153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576190295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1576190295
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1028850577
Short name T171
Test name
Test status
Simulation time 152318151 ps
CPU time 0.91 seconds
Started Apr 25 12:43:48 PM PDT 24
Finished Apr 25 12:43:50 PM PDT 24
Peak memory 196332 kb
Host smart-8295b2ff-73e3-4849-bfe2-f8f13ee3e891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028850577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1028850577
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3182219920
Short name T127
Test name
Test status
Simulation time 49534224 ps
CPU time 1.04 seconds
Started Apr 25 12:43:46 PM PDT 24
Finished Apr 25 12:43:48 PM PDT 24
Peak memory 196480 kb
Host smart-c071fb17-ce2f-41ca-b0da-d3f02ca9508d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182219920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3182219920
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1276483256
Short name T422
Test name
Test status
Simulation time 111863561677 ps
CPU time 144.74 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 12:46:21 PM PDT 24
Peak memory 198148 kb
Host smart-5a72a5d2-772b-4de0-9efc-352bad1b579c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276483256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1276483256
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2408750800
Short name T633
Test name
Test status
Simulation time 60468516102 ps
CPU time 1642.18 seconds
Started Apr 25 12:43:45 PM PDT 24
Finished Apr 25 01:11:09 PM PDT 24
Peak memory 198312 kb
Host smart-80f395ae-5206-4a2a-a2c9-fa2d47baeb3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2408750800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2408750800
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2750965271
Short name T412
Test name
Test status
Simulation time 14722336 ps
CPU time 0.58 seconds
Started Apr 25 12:43:51 PM PDT 24
Finished Apr 25 12:43:53 PM PDT 24
Peak memory 193900 kb
Host smart-e524e268-bc66-4445-a8c8-7d0f0944e718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750965271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2750965271
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4046875291
Short name T592
Test name
Test status
Simulation time 30788311 ps
CPU time 0.77 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:07 PM PDT 24
Peak memory 195212 kb
Host smart-f2aaf194-5ddd-41be-ab35-1e337600f3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046875291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4046875291
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1056993013
Short name T240
Test name
Test status
Simulation time 1450981664 ps
CPU time 25.41 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:25 PM PDT 24
Peak memory 196936 kb
Host smart-12b91496-cb42-42f7-8c74-95a8ca6325a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056993013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1056993013
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1559401859
Short name T685
Test name
Test status
Simulation time 248031143 ps
CPU time 0.92 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 12:43:57 PM PDT 24
Peak memory 197244 kb
Host smart-0ccde72d-4a43-4457-b7f6-15fc4e20cd1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559401859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1559401859
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.778162736
Short name T621
Test name
Test status
Simulation time 75163655 ps
CPU time 1.3 seconds
Started Apr 25 12:43:49 PM PDT 24
Finished Apr 25 12:43:52 PM PDT 24
Peak memory 197312 kb
Host smart-b486d1ef-1481-45b4-81b1-28b6bb151f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778162736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.778162736
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2520030657
Short name T295
Test name
Test status
Simulation time 476231807 ps
CPU time 1.67 seconds
Started Apr 25 12:43:42 PM PDT 24
Finished Apr 25 12:43:46 PM PDT 24
Peak memory 196400 kb
Host smart-95476695-b148-4044-bd54-5c78ec351420
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520030657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2520030657
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3883690438
Short name T544
Test name
Test status
Simulation time 175071835 ps
CPU time 2.46 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:44:00 PM PDT 24
Peak memory 197236 kb
Host smart-4ab5b6a8-4c11-4bac-9194-c84a48980811
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883690438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3883690438
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.436981238
Short name T470
Test name
Test status
Simulation time 206805996 ps
CPU time 1 seconds
Started Apr 25 12:43:43 PM PDT 24
Finished Apr 25 12:43:45 PM PDT 24
Peak memory 196672 kb
Host smart-21e9528b-7fe7-4d79-8417-f4cccfc38bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436981238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.436981238
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3757713194
Short name T652
Test name
Test status
Simulation time 66570473 ps
CPU time 1.17 seconds
Started Apr 25 12:43:56 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 197096 kb
Host smart-717296d2-ae19-4c1c-afdc-a18f1a70fab2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757713194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3757713194
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.83744103
Short name T635
Test name
Test status
Simulation time 121689027 ps
CPU time 5.4 seconds
Started Apr 25 12:43:45 PM PDT 24
Finished Apr 25 12:43:52 PM PDT 24
Peak memory 198060 kb
Host smart-b2c74f7d-563e-4a67-afd4-9dedc7497caa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83744103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand
om_long_reg_writes_reg_reads.83744103
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3500676021
Short name T471
Test name
Test status
Simulation time 254233910 ps
CPU time 1.19 seconds
Started Apr 25 12:43:58 PM PDT 24
Finished Apr 25 12:44:01 PM PDT 24
Peak memory 196032 kb
Host smart-2dc4412f-ae31-4dc2-8421-a735089fc18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500676021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3500676021
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2391862877
Short name T235
Test name
Test status
Simulation time 83720941 ps
CPU time 0.79 seconds
Started Apr 25 12:43:40 PM PDT 24
Finished Apr 25 12:43:42 PM PDT 24
Peak memory 195212 kb
Host smart-596004c0-4942-45fd-b249-7ddbb7ff68c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391862877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2391862877
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3370924343
Short name T229
Test name
Test status
Simulation time 7201575685 ps
CPU time 95.4 seconds
Started Apr 25 12:43:59 PM PDT 24
Finished Apr 25 12:45:36 PM PDT 24
Peak memory 198128 kb
Host smart-3e18509e-549e-4a5c-90ea-e197fab45e73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370924343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3370924343
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1173249901
Short name T321
Test name
Test status
Simulation time 30517792439 ps
CPU time 688.36 seconds
Started Apr 25 12:43:58 PM PDT 24
Finished Apr 25 12:55:28 PM PDT 24
Peak memory 198256 kb
Host smart-37fcc12d-ae03-4451-ad55-7f1afc535fdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1173249901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1173249901
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3147718016
Short name T18
Test name
Test status
Simulation time 74947202 ps
CPU time 0.55 seconds
Started Apr 25 12:44:02 PM PDT 24
Finished Apr 25 12:44:04 PM PDT 24
Peak memory 193900 kb
Host smart-0b1069f8-2526-47ff-baf7-021b101b4014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147718016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3147718016
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3952106187
Short name T153
Test name
Test status
Simulation time 142465033 ps
CPU time 0.69 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 194284 kb
Host smart-31b71a22-5da7-457f-90c0-19432fd6db80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952106187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3952106187
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3113285670
Short name T271
Test name
Test status
Simulation time 144886055 ps
CPU time 7.73 seconds
Started Apr 25 12:43:52 PM PDT 24
Finished Apr 25 12:44:01 PM PDT 24
Peak memory 196440 kb
Host smart-e7f17d66-eb7a-438c-9f88-4b6f974d6188
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113285670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3113285670
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1334428942
Short name T690
Test name
Test status
Simulation time 65948955 ps
CPU time 0.81 seconds
Started Apr 25 12:44:10 PM PDT 24
Finished Apr 25 12:44:15 PM PDT 24
Peak memory 196064 kb
Host smart-f55686a5-dc09-43a6-86a6-c8799d093a79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334428942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1334428942
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1522444931
Short name T190
Test name
Test status
Simulation time 81799834 ps
CPU time 1.12 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 12:43:56 PM PDT 24
Peak memory 195844 kb
Host smart-a22612d1-fde5-4a2f-9949-b1906931f1aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522444931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1522444931
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3939823667
Short name T676
Test name
Test status
Simulation time 59814808 ps
CPU time 1.54 seconds
Started Apr 25 12:43:59 PM PDT 24
Finished Apr 25 12:44:02 PM PDT 24
Peak memory 196660 kb
Host smart-593de1fa-2219-400e-8be1-cc0ac45952b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939823667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3939823667
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3704136988
Short name T150
Test name
Test status
Simulation time 90206656 ps
CPU time 0.74 seconds
Started Apr 25 12:43:43 PM PDT 24
Finished Apr 25 12:43:46 PM PDT 24
Peak memory 195480 kb
Host smart-792daeca-4e63-4711-9b1a-4eb83c6e9713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704136988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3704136988
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3758330519
Short name T678
Test name
Test status
Simulation time 36831369 ps
CPU time 0.89 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 195940 kb
Host smart-098e8a9e-efe2-4611-a73f-e55bdbb13761
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758330519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3758330519
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2616362284
Short name T452
Test name
Test status
Simulation time 713260008 ps
CPU time 2.52 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:44:00 PM PDT 24
Peak memory 198020 kb
Host smart-92d1050e-f294-46c3-acea-4874becf86f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616362284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2616362284
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2837719791
Short name T117
Test name
Test status
Simulation time 32833553 ps
CPU time 1 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:01 PM PDT 24
Peak memory 195568 kb
Host smart-c9f1ed59-0b68-47de-9139-9d20cc97853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837719791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2837719791
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2726270101
Short name T196
Test name
Test status
Simulation time 139035623 ps
CPU time 1.19 seconds
Started Apr 25 12:43:48 PM PDT 24
Finished Apr 25 12:43:50 PM PDT 24
Peak memory 196672 kb
Host smart-4288aac2-94b4-4a85-8642-b4b854db7a8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726270101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2726270101
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3680900550
Short name T351
Test name
Test status
Simulation time 17137440183 ps
CPU time 102.11 seconds
Started Apr 25 12:44:05 PM PDT 24
Finished Apr 25 12:45:49 PM PDT 24
Peak memory 198220 kb
Host smart-2d5efc01-adff-49a6-99a0-2c557a3e89c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680900550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3680900550
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.825668006
Short name T69
Test name
Test status
Simulation time 148090377299 ps
CPU time 883.94 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:58:43 PM PDT 24
Peak memory 198296 kb
Host smart-87cdb1a5-51b4-4feb-a01c-301902058c7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=825668006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.825668006
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2923307777
Short name T607
Test name
Test status
Simulation time 82312223 ps
CPU time 0.54 seconds
Started Apr 25 12:44:05 PM PDT 24
Finished Apr 25 12:44:08 PM PDT 24
Peak memory 194620 kb
Host smart-57ab7986-d212-4e7d-8db6-bc2c27689af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923307777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2923307777
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2065533688
Short name T63
Test name
Test status
Simulation time 239967927 ps
CPU time 0.73 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:43:58 PM PDT 24
Peak memory 196036 kb
Host smart-fb2665fd-743e-4c04-83bc-21d1983a7add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065533688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2065533688
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2635057112
Short name T349
Test name
Test status
Simulation time 4092884485 ps
CPU time 7.6 seconds
Started Apr 25 12:43:58 PM PDT 24
Finished Apr 25 12:44:08 PM PDT 24
Peak memory 196852 kb
Host smart-c98a31d6-6cfc-48e7-a79c-54a84250a526
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635057112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2635057112
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.611850230
Short name T121
Test name
Test status
Simulation time 522444901 ps
CPU time 0.97 seconds
Started Apr 25 12:43:49 PM PDT 24
Finished Apr 25 12:43:51 PM PDT 24
Peak memory 197920 kb
Host smart-032d327f-fb20-421a-8df6-3cc163150faa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611850230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.611850230
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.259056924
Short name T560
Test name
Test status
Simulation time 358217884 ps
CPU time 1.25 seconds
Started Apr 25 12:43:53 PM PDT 24
Finished Apr 25 12:43:56 PM PDT 24
Peak memory 197912 kb
Host smart-a6a4962a-b315-4b01-9786-8442a7f2d192
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259056924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.259056924
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.4242067533
Short name T387
Test name
Test status
Simulation time 137509115 ps
CPU time 1.55 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:01 PM PDT 24
Peak memory 196796 kb
Host smart-56d75e74-f162-40a7-b959-24121494b75f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242067533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.4242067533
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1930152995
Short name T557
Test name
Test status
Simulation time 53097471 ps
CPU time 1.17 seconds
Started Apr 25 12:43:46 PM PDT 24
Finished Apr 25 12:43:49 PM PDT 24
Peak memory 195640 kb
Host smart-d76cd5b2-fec7-4a67-b8d2-e7d6a49840c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930152995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1930152995
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2283648783
Short name T393
Test name
Test status
Simulation time 29482903 ps
CPU time 0.87 seconds
Started Apr 25 12:43:51 PM PDT 24
Finished Apr 25 12:43:53 PM PDT 24
Peak memory 196344 kb
Host smart-1525cb69-ef5b-46b6-95da-8fdecd8f9d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283648783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2283648783
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3158315399
Short name T148
Test name
Test status
Simulation time 15148837 ps
CPU time 0.69 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 195476 kb
Host smart-269cc122-8e41-4144-b85a-bd3d07d3ab3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158315399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3158315399
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2932497024
Short name T205
Test name
Test status
Simulation time 101167911 ps
CPU time 4.69 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:12 PM PDT 24
Peak memory 198016 kb
Host smart-e30b7ae9-f4c3-405a-8326-71bafbfce8cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932497024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2932497024
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1244097811
Short name T170
Test name
Test status
Simulation time 49847159 ps
CPU time 0.91 seconds
Started Apr 25 12:43:44 PM PDT 24
Finished Apr 25 12:43:47 PM PDT 24
Peak memory 196296 kb
Host smart-392dfade-a6bf-42c7-9770-451715b64443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244097811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1244097811
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.422859028
Short name T500
Test name
Test status
Simulation time 355160814 ps
CPU time 1.12 seconds
Started Apr 25 12:43:58 PM PDT 24
Finished Apr 25 12:44:01 PM PDT 24
Peak memory 195540 kb
Host smart-986f7e7b-bbbb-485c-bb21-f0a08b1e7913
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422859028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.422859028
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3019744961
Short name T703
Test name
Test status
Simulation time 76756467480 ps
CPU time 170.51 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:47:02 PM PDT 24
Peak memory 198128 kb
Host smart-7502f7c5-4b51-4f68-970c-0041ee12478c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019744961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3019744961
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2460192836
Short name T362
Test name
Test status
Simulation time 77596329486 ps
CPU time 1955.92 seconds
Started Apr 25 12:44:02 PM PDT 24
Finished Apr 25 01:16:40 PM PDT 24
Peak memory 198260 kb
Host smart-0bbb37a0-86fc-41f7-b84d-94659343636f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2460192836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2460192836
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1979201049
Short name T247
Test name
Test status
Simulation time 19751564 ps
CPU time 0.55 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:11 PM PDT 24
Peak memory 193988 kb
Host smart-3c769ace-f1b5-4130-8a2f-8790e280c945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979201049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1979201049
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1422231519
Short name T358
Test name
Test status
Simulation time 99145698 ps
CPU time 0.9 seconds
Started Apr 25 12:43:53 PM PDT 24
Finished Apr 25 12:43:55 PM PDT 24
Peak memory 196452 kb
Host smart-6567e400-8487-4263-bc53-9a6558d567de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422231519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1422231519
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.4265358622
Short name T665
Test name
Test status
Simulation time 206591877 ps
CPU time 3.88 seconds
Started Apr 25 12:43:56 PM PDT 24
Finished Apr 25 12:44:07 PM PDT 24
Peak memory 195724 kb
Host smart-d38ec665-6503-446a-8d02-1b40f811a10d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265358622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.4265358622
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3117005930
Short name T708
Test name
Test status
Simulation time 116914817 ps
CPU time 0.74 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:43:58 PM PDT 24
Peak memory 194708 kb
Host smart-bcb4cd70-c8b2-42b1-a08c-f2476210df10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117005930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3117005930
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3902216405
Short name T151
Test name
Test status
Simulation time 25310455 ps
CPU time 0.79 seconds
Started Apr 25 12:43:50 PM PDT 24
Finished Apr 25 12:43:51 PM PDT 24
Peak memory 195704 kb
Host smart-73fcc398-cf2f-4b0e-bdc4-d8a902bfcfb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902216405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3902216405
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.489914180
Short name T264
Test name
Test status
Simulation time 51655194 ps
CPU time 2.13 seconds
Started Apr 25 12:43:59 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 198068 kb
Host smart-cfbda1d1-d50a-4789-b12d-09073e39c05e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489914180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.489914180
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3748899399
Short name T267
Test name
Test status
Simulation time 79979010 ps
CPU time 1.93 seconds
Started Apr 25 12:43:50 PM PDT 24
Finished Apr 25 12:43:53 PM PDT 24
Peak memory 196476 kb
Host smart-9fedb9e0-1ab9-420a-a6cc-a7b015cdd42d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748899399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3748899399
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2643337913
Short name T552
Test name
Test status
Simulation time 51460788 ps
CPU time 0.68 seconds
Started Apr 25 12:43:56 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 194496 kb
Host smart-a1870b35-d16a-4cdd-909a-1be05f08c3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643337913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2643337913
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.943117390
Short name T579
Test name
Test status
Simulation time 51325777 ps
CPU time 0.73 seconds
Started Apr 25 12:43:49 PM PDT 24
Finished Apr 25 12:43:50 PM PDT 24
Peak memory 196188 kb
Host smart-8d99f097-bd76-4e94-87b2-472e9e688252
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943117390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.943117390
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1689055563
Short name T404
Test name
Test status
Simulation time 365267184 ps
CPU time 4.22 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 12:44:00 PM PDT 24
Peak memory 197984 kb
Host smart-ef43d4cd-a287-4c5e-b5c2-4fe4bf52c83f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689055563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1689055563
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1781884121
Short name T434
Test name
Test status
Simulation time 40567285 ps
CPU time 1.17 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:03 PM PDT 24
Peak memory 196572 kb
Host smart-17f01724-94b9-4a38-92bc-624c352424a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781884121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1781884121
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2906366796
Short name T158
Test name
Test status
Simulation time 161884437 ps
CPU time 0.93 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:07 PM PDT 24
Peak memory 195760 kb
Host smart-bf1f5c79-c000-4b57-9225-26581329b916
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906366796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2906366796
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.707497427
Short name T141
Test name
Test status
Simulation time 13460638533 ps
CPU time 78.75 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:45:16 PM PDT 24
Peak memory 198244 kb
Host smart-4c3b2011-cfed-4dbc-a163-c69ee22671aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707497427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.707497427
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3233472551
Short name T447
Test name
Test status
Simulation time 14216362 ps
CPU time 0.57 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:08 PM PDT 24
Peak memory 194596 kb
Host smart-6b9e0310-56a9-40e4-8dbb-49d2d1f47d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233472551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3233472551
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3516121004
Short name T493
Test name
Test status
Simulation time 114915449 ps
CPU time 0.86 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:43:58 PM PDT 24
Peak memory 195836 kb
Host smart-d386a826-a43d-46e6-b740-9c1a7a0f808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516121004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3516121004
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.4012396799
Short name T663
Test name
Test status
Simulation time 1891832697 ps
CPU time 22.49 seconds
Started Apr 25 12:43:48 PM PDT 24
Finished Apr 25 12:44:12 PM PDT 24
Peak memory 196252 kb
Host smart-ac853efa-4585-449a-ab8a-ded1924f0a9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012396799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.4012396799
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.314852850
Short name T304
Test name
Test status
Simulation time 52746582 ps
CPU time 0.9 seconds
Started Apr 25 12:43:54 PM PDT 24
Finished Apr 25 12:43:57 PM PDT 24
Peak memory 198012 kb
Host smart-05985538-8a34-4fc5-97f6-aae18b20aca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314852850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.314852850
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.423169905
Short name T699
Test name
Test status
Simulation time 203588019 ps
CPU time 1.33 seconds
Started Apr 25 12:44:13 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 196912 kb
Host smart-a2c72d30-453b-4f03-ba99-0a44f4c94600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423169905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.423169905
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.469918278
Short name T146
Test name
Test status
Simulation time 75210800 ps
CPU time 2.79 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 196360 kb
Host smart-012a089a-35ec-4a99-851e-e4b1dabe284f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469918278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.469918278
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1209530897
Short name T529
Test name
Test status
Simulation time 498017447 ps
CPU time 2.64 seconds
Started Apr 25 12:43:59 PM PDT 24
Finished Apr 25 12:44:04 PM PDT 24
Peak memory 196464 kb
Host smart-6793536c-b64d-453b-9f56-50a6691296a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209530897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1209530897
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2448147346
Short name T625
Test name
Test status
Simulation time 162140003 ps
CPU time 1.03 seconds
Started Apr 25 12:43:52 PM PDT 24
Finished Apr 25 12:43:54 PM PDT 24
Peak memory 196544 kb
Host smart-f0c2aa92-300c-4465-a554-57b9cc2a1a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448147346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2448147346
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3699507810
Short name T587
Test name
Test status
Simulation time 106925597 ps
CPU time 0.85 seconds
Started Apr 25 12:43:49 PM PDT 24
Finished Apr 25 12:43:51 PM PDT 24
Peak memory 196660 kb
Host smart-888005fb-a48a-4353-8338-1006a8ebd1f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699507810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3699507810
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1652948563
Short name T3
Test name
Test status
Simulation time 3098128661 ps
CPU time 5.61 seconds
Started Apr 25 12:43:49 PM PDT 24
Finished Apr 25 12:43:55 PM PDT 24
Peak memory 198144 kb
Host smart-729dc0da-c9c5-43e3-a94d-9b1a25346037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652948563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1652948563
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2025771019
Short name T681
Test name
Test status
Simulation time 41853021 ps
CPU time 1.19 seconds
Started Apr 25 12:43:52 PM PDT 24
Finished Apr 25 12:43:54 PM PDT 24
Peak memory 198012 kb
Host smart-d5958cc7-94e7-4037-bc9e-9919c020f607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025771019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2025771019
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1391429228
Short name T214
Test name
Test status
Simulation time 781789405 ps
CPU time 1.13 seconds
Started Apr 25 12:44:11 PM PDT 24
Finished Apr 25 12:44:16 PM PDT 24
Peak memory 195708 kb
Host smart-26a774d5-00bd-46f6-ad53-d46a537b61aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391429228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1391429228
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1956879343
Short name T315
Test name
Test status
Simulation time 6833368846 ps
CPU time 51.29 seconds
Started Apr 25 12:43:56 PM PDT 24
Finished Apr 25 12:44:49 PM PDT 24
Peak memory 198196 kb
Host smart-d515f25a-b499-43c4-aeab-646efe890ded
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956879343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1956879343
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2533325830
Short name T683
Test name
Test status
Simulation time 79750241 ps
CPU time 0.56 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:06 PM PDT 24
Peak memory 194660 kb
Host smart-a6457fe0-0188-468b-8932-41247211f8af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533325830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2533325830
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3259047079
Short name T391
Test name
Test status
Simulation time 23708623 ps
CPU time 0.68 seconds
Started Apr 25 12:43:52 PM PDT 24
Finished Apr 25 12:43:53 PM PDT 24
Peak memory 194236 kb
Host smart-ea0ce357-c5e8-4b8a-b80d-8f7b02126e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259047079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3259047079
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.307993832
Short name T207
Test name
Test status
Simulation time 737283567 ps
CPU time 12.09 seconds
Started Apr 25 12:44:18 PM PDT 24
Finished Apr 25 12:44:33 PM PDT 24
Peak memory 197044 kb
Host smart-b291b741-f72a-4a7f-9394-f27fff6175d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307993832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.307993832
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1464509917
Short name T630
Test name
Test status
Simulation time 32077461 ps
CPU time 0.68 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:00 PM PDT 24
Peak memory 194772 kb
Host smart-d08a1f85-5b81-429e-bec8-7ee87e79f018
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464509917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1464509917
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.329876850
Short name T203
Test name
Test status
Simulation time 203420355 ps
CPU time 1.37 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:44:13 PM PDT 24
Peak memory 195844 kb
Host smart-0658ecd8-2ab3-47a4-bb49-3fb92fe75d31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329876850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.329876850
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1403176393
Short name T403
Test name
Test status
Simulation time 302163254 ps
CPU time 3.05 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:13 PM PDT 24
Peak memory 198060 kb
Host smart-d35aaf87-1396-4e77-b313-4e319a3ba7b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403176393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1403176393
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1596423559
Short name T373
Test name
Test status
Simulation time 108147988 ps
CPU time 2.45 seconds
Started Apr 25 12:44:05 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 195880 kb
Host smart-5b58b590-af25-4789-a45f-54f677121041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596423559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1596423559
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3863492552
Short name T565
Test name
Test status
Simulation time 111446139 ps
CPU time 1.26 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 195816 kb
Host smart-711b1a05-873a-43d7-b016-8e5d051e7460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863492552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3863492552
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1848055522
Short name T697
Test name
Test status
Simulation time 184739310 ps
CPU time 1.12 seconds
Started Apr 25 12:43:53 PM PDT 24
Finished Apr 25 12:43:56 PM PDT 24
Peak memory 196632 kb
Host smart-69fd0cb9-8b52-4e48-a682-71f50d9ed08f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848055522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1848055522
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.4001555762
Short name T672
Test name
Test status
Simulation time 64521096 ps
CPU time 2.62 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:05 PM PDT 24
Peak memory 198000 kb
Host smart-93b62999-043c-4a01-88de-60996169d1bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001555762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.4001555762
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3861843349
Short name T585
Test name
Test status
Simulation time 66390611 ps
CPU time 1.18 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 196484 kb
Host smart-3254af5a-3a19-4a98-b653-35ca9ab2f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861843349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3861843349
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2195031953
Short name T280
Test name
Test status
Simulation time 87025405 ps
CPU time 1.18 seconds
Started Apr 25 12:44:05 PM PDT 24
Finished Apr 25 12:44:08 PM PDT 24
Peak memory 196448 kb
Host smart-e1be8ace-f344-4801-91c1-a903fa7801e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195031953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2195031953
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2881904237
Short name T429
Test name
Test status
Simulation time 19167961266 ps
CPU time 184.13 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:47:01 PM PDT 24
Peak memory 198148 kb
Host smart-87e30078-0a9e-415c-985c-da043a64d760
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881904237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2881904237
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2222646232
Short name T451
Test name
Test status
Simulation time 202198222025 ps
CPU time 1875.89 seconds
Started Apr 25 12:43:51 PM PDT 24
Finished Apr 25 01:15:13 PM PDT 24
Peak memory 198296 kb
Host smart-58cc81ce-3d19-4caf-aba7-0ceae359dab8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2222646232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2222646232
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2274568172
Short name T184
Test name
Test status
Simulation time 153320944 ps
CPU time 0.58 seconds
Started Apr 25 12:43:53 PM PDT 24
Finished Apr 25 12:43:55 PM PDT 24
Peak memory 193984 kb
Host smart-2d0d3da6-ca21-4ae7-99c3-798a8a423e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274568172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2274568172
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1836319160
Short name T347
Test name
Test status
Simulation time 246158985 ps
CPU time 0.68 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 194220 kb
Host smart-26160dc8-f72d-4265-8693-ca4d1e2cf4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836319160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1836319160
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2624440664
Short name T553
Test name
Test status
Simulation time 1831374605 ps
CPU time 23.05 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:44:34 PM PDT 24
Peak memory 198024 kb
Host smart-1221ce5a-bc0e-4b96-871b-3de9fb5d7e33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624440664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2624440664
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3708689719
Short name T519
Test name
Test status
Simulation time 174799345 ps
CPU time 0.75 seconds
Started Apr 25 12:43:55 PM PDT 24
Finished Apr 25 12:43:57 PM PDT 24
Peak memory 195780 kb
Host smart-052b5bea-e4a6-4f51-83d4-a49a4a885124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708689719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3708689719
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2094450680
Short name T113
Test name
Test status
Simulation time 466397307 ps
CPU time 1.42 seconds
Started Apr 25 12:43:56 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 197024 kb
Host smart-28e8613b-ae21-4dc9-9c24-42293d0de7cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094450680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2094450680
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2543315053
Short name T388
Test name
Test status
Simulation time 304719317 ps
CPU time 3.21 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:02 PM PDT 24
Peak memory 198076 kb
Host smart-977fd7d5-3232-4178-ac3c-37b028dbe28e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543315053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2543315053
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3009556694
Short name T468
Test name
Test status
Simulation time 212654432 ps
CPU time 1.46 seconds
Started Apr 25 12:44:09 PM PDT 24
Finished Apr 25 12:44:14 PM PDT 24
Peak memory 196108 kb
Host smart-9c7a0d39-49ca-486c-80aa-7389389e8a7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009556694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3009556694
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1538359348
Short name T179
Test name
Test status
Simulation time 19974862 ps
CPU time 0.65 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:06 PM PDT 24
Peak memory 194408 kb
Host smart-3ad2b0e2-b538-42cc-b3de-d2f0b537e639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538359348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1538359348
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1005424567
Short name T517
Test name
Test status
Simulation time 78078205 ps
CPU time 0.68 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:07 PM PDT 24
Peak memory 194420 kb
Host smart-5978e4c7-4c44-44ef-ab15-7f39aa72e0a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005424567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1005424567
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3183256458
Short name T656
Test name
Test status
Simulation time 1186536722 ps
CPU time 5.01 seconds
Started Apr 25 12:44:02 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 197968 kb
Host smart-33740d45-3afd-4888-9669-287b388eb8c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183256458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3183256458
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.92595835
Short name T664
Test name
Test status
Simulation time 66427740 ps
CPU time 0.97 seconds
Started Apr 25 12:44:01 PM PDT 24
Finished Apr 25 12:44:04 PM PDT 24
Peak memory 195828 kb
Host smart-c973416a-a843-4814-ae5f-fe45fae4baf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92595835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.92595835
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.752750545
Short name T642
Test name
Test status
Simulation time 29517521 ps
CPU time 0.81 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:00 PM PDT 24
Peak memory 195344 kb
Host smart-ad5ab250-6681-4120-8d06-3f8a69c30a91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752750545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.752750545
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1875680446
Short name T497
Test name
Test status
Simulation time 16462873260 ps
CPU time 84.52 seconds
Started Apr 25 12:43:56 PM PDT 24
Finished Apr 25 12:45:23 PM PDT 24
Peak memory 198196 kb
Host smart-caf2ca89-6906-403c-ab2c-0d8d14f1e0f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875680446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1875680446
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1814757557
Short name T142
Test name
Test status
Simulation time 31929331 ps
CPU time 0.56 seconds
Started Apr 25 12:42:55 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 193904 kb
Host smart-2e3ec20d-ce9c-402e-8fdf-c055c8531354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814757557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1814757557
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.788050013
Short name T276
Test name
Test status
Simulation time 204044307 ps
CPU time 0.99 seconds
Started Apr 25 12:42:48 PM PDT 24
Finished Apr 25 12:42:52 PM PDT 24
Peak memory 195980 kb
Host smart-69b5d638-44f4-4de2-90dc-edc6c7a65863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788050013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.788050013
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1962882699
Short name T154
Test name
Test status
Simulation time 580598113 ps
CPU time 7.61 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 196816 kb
Host smart-959182aa-63c2-43c4-bd46-d941d543ba44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962882699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1962882699
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2520705171
Short name T572
Test name
Test status
Simulation time 152687582 ps
CPU time 0.88 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 196092 kb
Host smart-d7a71022-d4b3-430b-a544-295cf74ebc9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520705171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2520705171
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3240731704
Short name T700
Test name
Test status
Simulation time 59623199 ps
CPU time 1.02 seconds
Started Apr 25 12:42:48 PM PDT 24
Finished Apr 25 12:42:51 PM PDT 24
Peak memory 195824 kb
Host smart-a26ea3b5-9be3-4ad9-ac45-81ca374164fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240731704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3240731704
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2398590890
Short name T525
Test name
Test status
Simulation time 317835499 ps
CPU time 3.15 seconds
Started Apr 25 12:42:50 PM PDT 24
Finished Apr 25 12:42:57 PM PDT 24
Peak memory 198148 kb
Host smart-5566c0f7-8a31-4438-9cc6-cf73a5399c28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398590890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2398590890
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3882979172
Short name T670
Test name
Test status
Simulation time 27240244 ps
CPU time 1 seconds
Started Apr 25 12:42:49 PM PDT 24
Finished Apr 25 12:42:53 PM PDT 24
Peak memory 196340 kb
Host smart-0206cbee-9a49-482f-8bb0-5d3962ea8f25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882979172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3882979172
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2524620387
Short name T64
Test name
Test status
Simulation time 20610216 ps
CPU time 0.88 seconds
Started Apr 25 12:42:48 PM PDT 24
Finished Apr 25 12:42:51 PM PDT 24
Peak memory 196488 kb
Host smart-d6839b49-17e7-4d1a-9b0f-a24d7c8787b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524620387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2524620387
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.672571212
Short name T225
Test name
Test status
Simulation time 72859354 ps
CPU time 1.2 seconds
Started Apr 25 12:42:45 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 197052 kb
Host smart-700dbcdd-1b3c-4b3f-81f7-d9d07a9ce11f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672571212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.672571212
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2563987546
Short name T2
Test name
Test status
Simulation time 666160450 ps
CPU time 4.62 seconds
Started Apr 25 12:42:58 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 197996 kb
Host smart-97a86790-7442-4d23-ab19-852301817c2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563987546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2563987546
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2689956161
Short name T57
Test name
Test status
Simulation time 102868447 ps
CPU time 0.79 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:57 PM PDT 24
Peak memory 213780 kb
Host smart-e0d66786-7553-461c-89c1-5386a63ff03f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689956161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2689956161
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1534906150
Short name T455
Test name
Test status
Simulation time 126463907 ps
CPU time 0.94 seconds
Started Apr 25 12:42:45 PM PDT 24
Finished Apr 25 12:42:47 PM PDT 24
Peak memory 196400 kb
Host smart-063a31ac-25ec-4811-b30f-ceb395e55549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534906150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1534906150
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2284698662
Short name T400
Test name
Test status
Simulation time 37047378 ps
CPU time 1.15 seconds
Started Apr 25 12:43:16 PM PDT 24
Finished Apr 25 12:43:20 PM PDT 24
Peak memory 195448 kb
Host smart-0a0ad1cf-8a0c-43aa-9e38-91e111dd8ae6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284698662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2284698662
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2851210281
Short name T303
Test name
Test status
Simulation time 32402374486 ps
CPU time 197.13 seconds
Started Apr 25 12:42:50 PM PDT 24
Finished Apr 25 12:46:11 PM PDT 24
Peak memory 198240 kb
Host smart-a085b295-ca15-4009-a0ac-db66fb7d9eee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851210281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2851210281
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2913650495
Short name T567
Test name
Test status
Simulation time 46790050 ps
CPU time 0.59 seconds
Started Apr 25 12:43:59 PM PDT 24
Finished Apr 25 12:44:01 PM PDT 24
Peak memory 194840 kb
Host smart-a0fd2ae7-6dd9-4bae-984c-b2d3b4058feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913650495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2913650495
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.4274779079
Short name T204
Test name
Test status
Simulation time 59956373 ps
CPU time 0.75 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 195392 kb
Host smart-0d85a461-cc4b-4264-8561-e7a2a8998c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274779079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.4274779079
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1356278492
Short name T183
Test name
Test status
Simulation time 452953483 ps
CPU time 22.13 seconds
Started Apr 25 12:44:05 PM PDT 24
Finished Apr 25 12:44:29 PM PDT 24
Peak memory 195596 kb
Host smart-e3feaac4-5963-4e6c-b05c-2b5c5024c446
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356278492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1356278492
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1851566481
Short name T605
Test name
Test status
Simulation time 171094886 ps
CPU time 0.77 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:02 PM PDT 24
Peak memory 195472 kb
Host smart-0bedb671-4302-40a2-b8bc-a48df1214fcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851566481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1851566481
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2655645496
Short name T137
Test name
Test status
Simulation time 50759248 ps
CPU time 0.91 seconds
Started Apr 25 12:44:09 PM PDT 24
Finished Apr 25 12:44:14 PM PDT 24
Peak memory 196748 kb
Host smart-b51bd492-0fdf-4a25-8297-f4c4de571e18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655645496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2655645496
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.592842946
Short name T378
Test name
Test status
Simulation time 152835377 ps
CPU time 3.77 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:44:14 PM PDT 24
Peak memory 196264 kb
Host smart-35f9baa7-4b46-4494-a44a-0a6770be00a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592842946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.592842946
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3152875229
Short name T522
Test name
Test status
Simulation time 97859622 ps
CPU time 1.99 seconds
Started Apr 25 12:44:05 PM PDT 24
Finished Apr 25 12:44:08 PM PDT 24
Peak memory 196132 kb
Host smart-82dbe77e-b682-4e99-937e-6491d89e8a37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152875229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3152875229
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2476019737
Short name T341
Test name
Test status
Simulation time 85869450 ps
CPU time 0.81 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 196132 kb
Host smart-30fc4291-a99b-4fb5-a9c5-2d327da7ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476019737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2476019737
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1679625408
Short name T600
Test name
Test status
Simulation time 88028494 ps
CPU time 0.93 seconds
Started Apr 25 12:44:02 PM PDT 24
Finished Apr 25 12:44:05 PM PDT 24
Peak memory 196072 kb
Host smart-a67bc087-6546-4ac4-9105-a3e10401644e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679625408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1679625408
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.743125158
Short name T192
Test name
Test status
Simulation time 303260252 ps
CPU time 1.4 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:11 PM PDT 24
Peak memory 197956 kb
Host smart-29b494de-457d-42b3-98cb-ebca41df10e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743125158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.743125158
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1629437601
Short name T299
Test name
Test status
Simulation time 69248454 ps
CPU time 1.34 seconds
Started Apr 25 12:44:02 PM PDT 24
Finished Apr 25 12:44:05 PM PDT 24
Peak memory 198052 kb
Host smart-11477dda-0259-4f0b-8941-8606c1764ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629437601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1629437601
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3228382110
Short name T611
Test name
Test status
Simulation time 292855748 ps
CPU time 1.39 seconds
Started Apr 25 12:43:51 PM PDT 24
Finished Apr 25 12:43:53 PM PDT 24
Peak memory 196804 kb
Host smart-b5d309a4-242d-4144-ba83-9ef03b805428
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228382110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3228382110
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3795218222
Short name T458
Test name
Test status
Simulation time 25372623969 ps
CPU time 70.45 seconds
Started Apr 25 12:44:09 PM PDT 24
Finished Apr 25 12:45:23 PM PDT 24
Peak memory 198292 kb
Host smart-8e0463e3-c66a-49d8-96ae-2e8026c566ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795218222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3795218222
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1309541980
Short name T65
Test name
Test status
Simulation time 118011073930 ps
CPU time 1397.85 seconds
Started Apr 25 12:44:17 PM PDT 24
Finished Apr 25 01:07:38 PM PDT 24
Peak memory 198228 kb
Host smart-0bbaa3d5-2f1e-4b01-b9a1-cab9a6e7e2c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1309541980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1309541980
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1576216667
Short name T215
Test name
Test status
Simulation time 48845777 ps
CPU time 0.6 seconds
Started Apr 25 12:44:03 PM PDT 24
Finished Apr 25 12:44:05 PM PDT 24
Peak memory 194820 kb
Host smart-1c967af1-30c0-4350-b72f-9b1f75fae5d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576216667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1576216667
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1323100018
Short name T287
Test name
Test status
Simulation time 328706941 ps
CPU time 0.86 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:10 PM PDT 24
Peak memory 196348 kb
Host smart-3743cfc6-bd81-4e2d-84e1-3dcbcea12775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323100018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1323100018
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.531996214
Short name T440
Test name
Test status
Simulation time 1605268169 ps
CPU time 28.21 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:36 PM PDT 24
Peak memory 197996 kb
Host smart-066e7c83-cc33-49d5-85f9-42554b9d6af2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531996214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.531996214
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3486602276
Short name T539
Test name
Test status
Simulation time 72959277 ps
CPU time 1 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:44:13 PM PDT 24
Peak memory 196356 kb
Host smart-353e00a0-f7a1-4042-839a-bc7ac9a8b497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486602276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3486602276
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2680943650
Short name T272
Test name
Test status
Simulation time 1296557587 ps
CPU time 1.4 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:10 PM PDT 24
Peak memory 197204 kb
Host smart-9d95f8e9-e242-4001-bf2a-965dc6de5f38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680943650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2680943650
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1215455343
Short name T658
Test name
Test status
Simulation time 81421252 ps
CPU time 0.97 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:11 PM PDT 24
Peak memory 196256 kb
Host smart-888e2b53-5a04-4e3f-adc6-6a3de425694b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215455343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1215455343
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3717966098
Short name T669
Test name
Test status
Simulation time 251576566 ps
CPU time 3.47 seconds
Started Apr 25 12:43:56 PM PDT 24
Finished Apr 25 12:44:02 PM PDT 24
Peak memory 197072 kb
Host smart-c71304c6-14f9-4bcb-a710-ef72dd0c3c59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717966098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3717966098
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1975186415
Short name T38
Test name
Test status
Simulation time 65721703 ps
CPU time 0.91 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:09 PM PDT 24
Peak memory 196568 kb
Host smart-8e1fd891-733f-49fa-bb17-43588054e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975186415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1975186415
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1720142411
Short name T251
Test name
Test status
Simulation time 27246873 ps
CPU time 0.69 seconds
Started Apr 25 12:43:57 PM PDT 24
Finished Apr 25 12:44:00 PM PDT 24
Peak memory 195500 kb
Host smart-4b08cd92-ca4a-4cc5-853d-a382bc33ba5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720142411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1720142411
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.301697504
Short name T601
Test name
Test status
Simulation time 1247446980 ps
CPU time 4.78 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:07 PM PDT 24
Peak memory 198060 kb
Host smart-7a4f6c30-465c-4ec0-b878-18bccadce726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301697504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.301697504
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.341321599
Short name T14
Test name
Test status
Simulation time 78554978 ps
CPU time 1.2 seconds
Started Apr 25 12:43:56 PM PDT 24
Finished Apr 25 12:43:59 PM PDT 24
Peak memory 195568 kb
Host smart-d3895e36-5bb1-46cc-8471-1e48ace98763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341321599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.341321599
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3281960524
Short name T406
Test name
Test status
Simulation time 149003118 ps
CPU time 1.01 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:44:12 PM PDT 24
Peak memory 196560 kb
Host smart-8d81e557-2460-4add-a836-3cd7b6852bb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281960524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3281960524
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3267274021
Short name T164
Test name
Test status
Simulation time 7613185384 ps
CPU time 182.86 seconds
Started Apr 25 12:44:09 PM PDT 24
Finished Apr 25 12:47:15 PM PDT 24
Peak memory 198284 kb
Host smart-67491560-6ff5-419d-9b11-906a816406a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267274021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3267274021
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3964941614
Short name T466
Test name
Test status
Simulation time 324100819752 ps
CPU time 1769.82 seconds
Started Apr 25 12:44:20 PM PDT 24
Finished Apr 25 01:13:53 PM PDT 24
Peak memory 198200 kb
Host smart-44dbec00-7216-43cc-913f-e7d94917c4ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3964941614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3964941614
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1133404492
Short name T336
Test name
Test status
Simulation time 33048818 ps
CPU time 0.6 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:02 PM PDT 24
Peak memory 194140 kb
Host smart-298922ce-0f88-4542-9477-a68777a0023b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133404492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1133404492
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1909963171
Short name T31
Test name
Test status
Simulation time 54488604 ps
CPU time 0.89 seconds
Started Apr 25 12:44:12 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 196604 kb
Host smart-a564637c-25b6-43dc-a83c-9cce2e7f719c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909963171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1909963171
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1171810390
Short name T476
Test name
Test status
Simulation time 3546422780 ps
CPU time 14.48 seconds
Started Apr 25 12:44:23 PM PDT 24
Finished Apr 25 12:44:41 PM PDT 24
Peak memory 196884 kb
Host smart-3959b676-14f9-4e4f-8d03-067a8cb4199c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171810390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1171810390
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2148084513
Short name T561
Test name
Test status
Simulation time 128427557 ps
CPU time 0.72 seconds
Started Apr 25 12:44:14 PM PDT 24
Finished Apr 25 12:44:18 PM PDT 24
Peak memory 195496 kb
Host smart-21afdbf1-607e-4a74-a475-14768908a4e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148084513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2148084513
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.113051431
Short name T180
Test name
Test status
Simulation time 67821959 ps
CPU time 1.1 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:06 PM PDT 24
Peak memory 196748 kb
Host smart-991a3d2b-2164-44a6-9e2f-27d3217b32ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113051431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.113051431
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1440466638
Short name T189
Test name
Test status
Simulation time 89770878 ps
CPU time 3.61 seconds
Started Apr 25 12:44:21 PM PDT 24
Finished Apr 25 12:44:28 PM PDT 24
Peak memory 198188 kb
Host smart-870c885a-dc1f-4a4f-9544-1483398ec2d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440466638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1440466638
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1481718213
Short name T284
Test name
Test status
Simulation time 116085286 ps
CPU time 0.89 seconds
Started Apr 25 12:44:14 PM PDT 24
Finished Apr 25 12:44:18 PM PDT 24
Peak memory 194512 kb
Host smart-b402f443-ee25-4613-9fdf-30ea7a376b54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481718213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1481718213
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3040786682
Short name T29
Test name
Test status
Simulation time 50530693 ps
CPU time 0.66 seconds
Started Apr 25 12:44:13 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 194292 kb
Host smart-5f989a42-610c-4fc6-a74a-ae9550c10231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040786682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3040786682
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.444359188
Short name T291
Test name
Test status
Simulation time 21489944 ps
CPU time 0.67 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:10 PM PDT 24
Peak memory 194388 kb
Host smart-bc1b786c-40f8-4fff-b25c-20d5314cdb79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444359188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.444359188
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.973638906
Short name T692
Test name
Test status
Simulation time 1319427833 ps
CPU time 4.54 seconds
Started Apr 25 12:44:11 PM PDT 24
Finished Apr 25 12:44:20 PM PDT 24
Peak memory 197972 kb
Host smart-163ea3d1-980f-48c5-b9b8-7c2131c40438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973638906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.973638906
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2210813370
Short name T461
Test name
Test status
Simulation time 69963960 ps
CPU time 1.17 seconds
Started Apr 25 12:44:18 PM PDT 24
Finished Apr 25 12:44:22 PM PDT 24
Peak memory 195572 kb
Host smart-e374c604-bd02-49b5-8358-b2e0bd864e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210813370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2210813370
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.467373522
Short name T636
Test name
Test status
Simulation time 33369407 ps
CPU time 0.91 seconds
Started Apr 25 12:44:16 PM PDT 24
Finished Apr 25 12:44:20 PM PDT 24
Peak memory 195476 kb
Host smart-98ad773d-2ccc-4d22-8910-5f1cebbb8385
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467373522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.467373522
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.552049561
Short name T340
Test name
Test status
Simulation time 22442682215 ps
CPU time 158.81 seconds
Started Apr 25 12:43:58 PM PDT 24
Finished Apr 25 12:46:39 PM PDT 24
Peak memory 198216 kb
Host smart-d06b6b60-7094-4a91-a3b6-2eb42453e3d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552049561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.552049561
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1694266422
Short name T615
Test name
Test status
Simulation time 23933765 ps
CPU time 0.57 seconds
Started Apr 25 12:44:09 PM PDT 24
Finished Apr 25 12:44:13 PM PDT 24
Peak memory 194680 kb
Host smart-f6e148ea-5037-4784-8d25-93cff7e5dbb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694266422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1694266422
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1667895273
Short name T275
Test name
Test status
Simulation time 29890798 ps
CPU time 0.75 seconds
Started Apr 25 12:44:04 PM PDT 24
Finished Apr 25 12:44:06 PM PDT 24
Peak memory 195388 kb
Host smart-8fdae673-d2ec-447c-a474-8d50f5663766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667895273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1667895273
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1759903884
Short name T597
Test name
Test status
Simulation time 3577845050 ps
CPU time 25.25 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:35 PM PDT 24
Peak memory 197056 kb
Host smart-0f17435e-7736-429e-9b1a-df05ae98259a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759903884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1759903884
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1371248208
Short name T22
Test name
Test status
Simulation time 211457809 ps
CPU time 0.85 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:10 PM PDT 24
Peak memory 196848 kb
Host smart-625644d5-4f36-4589-adbb-18705b68a7b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371248208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1371248208
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1610056458
Short name T399
Test name
Test status
Simulation time 63607939 ps
CPU time 1.03 seconds
Started Apr 25 12:44:09 PM PDT 24
Finished Apr 25 12:44:13 PM PDT 24
Peak memory 196164 kb
Host smart-6205b8a3-57b2-4d5a-ba2a-d5dcb6a1fd56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610056458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1610056458
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.211855603
Short name T307
Test name
Test status
Simulation time 225979953 ps
CPU time 3.32 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:44:14 PM PDT 24
Peak memory 198048 kb
Host smart-d0dda136-03f3-4b52-aa14-7ad8cf27e5a1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211855603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.211855603
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.245743915
Short name T568
Test name
Test status
Simulation time 681277693 ps
CPU time 3.36 seconds
Started Apr 25 12:44:00 PM PDT 24
Finished Apr 25 12:44:05 PM PDT 24
Peak memory 198136 kb
Host smart-417d3193-4659-42c0-b612-57cd768005ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245743915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
245743915
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3953676706
Short name T188
Test name
Test status
Simulation time 130183587 ps
CPU time 1.14 seconds
Started Apr 25 12:44:13 PM PDT 24
Finished Apr 25 12:44:18 PM PDT 24
Peak memory 196076 kb
Host smart-75d3d77b-4bc2-4b82-91a1-f87946448953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953676706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3953676706
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3924552081
Short name T463
Test name
Test status
Simulation time 33294328 ps
CPU time 1.13 seconds
Started Apr 25 12:44:19 PM PDT 24
Finished Apr 25 12:44:23 PM PDT 24
Peak memory 196700 kb
Host smart-94174b0d-441d-4c97-8543-c32586b74296
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924552081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3924552081
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2814974944
Short name T659
Test name
Test status
Simulation time 457136715 ps
CPU time 5.93 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:15 PM PDT 24
Peak memory 198056 kb
Host smart-4976cbcb-dbc3-4067-b880-37351ce7177d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814974944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2814974944
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.973018497
Short name T338
Test name
Test status
Simulation time 54154463 ps
CPU time 1.14 seconds
Started Apr 25 12:44:09 PM PDT 24
Finished Apr 25 12:44:13 PM PDT 24
Peak memory 195532 kb
Host smart-3727aaa2-ea50-41b3-b4cb-72ba709d3757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973018497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.973018497
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.4028463807
Short name T210
Test name
Test status
Simulation time 91469662 ps
CPU time 1.3 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:11 PM PDT 24
Peak memory 195548 kb
Host smart-f3d7f304-e662-4227-a4bb-fba76970f5e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028463807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.4028463807
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2191382882
Short name T168
Test name
Test status
Simulation time 1589381003 ps
CPU time 41.35 seconds
Started Apr 25 12:44:11 PM PDT 24
Finished Apr 25 12:44:57 PM PDT 24
Peak memory 197812 kb
Host smart-44a932d3-7bae-4812-a2da-1f10f6421f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191382882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2191382882
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2891236939
Short name T288
Test name
Test status
Simulation time 11781783 ps
CPU time 0.61 seconds
Started Apr 25 12:44:22 PM PDT 24
Finished Apr 25 12:44:26 PM PDT 24
Peak memory 194888 kb
Host smart-6024b48f-7f9b-469e-9db8-19160af2f897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891236939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2891236939
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3791874704
Short name T629
Test name
Test status
Simulation time 91314312 ps
CPU time 0.79 seconds
Started Apr 25 12:44:07 PM PDT 24
Finished Apr 25 12:44:11 PM PDT 24
Peak memory 196012 kb
Host smart-af7fe47f-f2d4-4df9-bd83-e1b699960f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791874704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3791874704
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1118708921
Short name T120
Test name
Test status
Simulation time 976689249 ps
CPU time 26.47 seconds
Started Apr 25 12:44:24 PM PDT 24
Finished Apr 25 12:44:54 PM PDT 24
Peak memory 196972 kb
Host smart-2408204c-f56d-4408-9fc8-32a8cd259c15
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118708921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1118708921
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3767965055
Short name T503
Test name
Test status
Simulation time 187432334 ps
CPU time 0.68 seconds
Started Apr 25 12:44:10 PM PDT 24
Finished Apr 25 12:44:14 PM PDT 24
Peak memory 194360 kb
Host smart-12790a28-428f-4199-a3af-9e766c078a18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767965055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3767965055
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3487196101
Short name T405
Test name
Test status
Simulation time 71011249 ps
CPU time 0.65 seconds
Started Apr 25 12:44:14 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 194440 kb
Host smart-a07075e8-101d-456b-a44c-321cc10a58db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487196101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3487196101
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.98297054
Short name T409
Test name
Test status
Simulation time 90691965 ps
CPU time 3.59 seconds
Started Apr 25 12:44:15 PM PDT 24
Finished Apr 25 12:44:22 PM PDT 24
Peak memory 198144 kb
Host smart-31f56695-7728-47a5-87b5-0bb4b922d87d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98297054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.gpio_intr_with_filter_rand_intr_event.98297054
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.645314744
Short name T477
Test name
Test status
Simulation time 51765133 ps
CPU time 0.95 seconds
Started Apr 25 12:44:12 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 195580 kb
Host smart-53b03bf7-3158-461b-a6f9-14b35486772c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645314744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
645314744
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.923288603
Short name T76
Test name
Test status
Simulation time 77665078 ps
CPU time 0.77 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:44:12 PM PDT 24
Peak memory 195420 kb
Host smart-a36bcf75-73ca-4bb9-ad86-4c51983c371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923288603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.923288603
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2769199383
Short name T637
Test name
Test status
Simulation time 509837584 ps
CPU time 1.07 seconds
Started Apr 25 12:44:06 PM PDT 24
Finished Apr 25 12:44:10 PM PDT 24
Peak memory 196044 kb
Host smart-95d35611-7647-468d-83eb-a40da6901fd9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769199383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2769199383
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2902096936
Short name T446
Test name
Test status
Simulation time 125154674 ps
CPU time 5.84 seconds
Started Apr 25 12:44:20 PM PDT 24
Finished Apr 25 12:44:29 PM PDT 24
Peak memory 198004 kb
Host smart-a61f6a15-a634-4f20-a309-ed631df2db1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902096936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2902096936
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.44933923
Short name T559
Test name
Test status
Simulation time 171094175 ps
CPU time 1.11 seconds
Started Apr 25 12:44:16 PM PDT 24
Finished Apr 25 12:44:20 PM PDT 24
Peak memory 195556 kb
Host smart-a1d5bc6b-f34f-477c-971f-0687136fb282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44933923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.44933923
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.104949884
Short name T457
Test name
Test status
Simulation time 392672068 ps
CPU time 1.57 seconds
Started Apr 25 12:44:03 PM PDT 24
Finished Apr 25 12:44:06 PM PDT 24
Peak memory 196776 kb
Host smart-a83b663f-b683-43ab-9e40-3c65ceb54bb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104949884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.104949884
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.774520705
Short name T510
Test name
Test status
Simulation time 4797902180 ps
CPU time 28.09 seconds
Started Apr 25 12:44:13 PM PDT 24
Finished Apr 25 12:44:45 PM PDT 24
Peak memory 198204 kb
Host smart-ccc94f31-21bd-455e-b760-96864aea542a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774520705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.774520705
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.4009694445
Short name T437
Test name
Test status
Simulation time 18824997 ps
CPU time 0.57 seconds
Started Apr 25 12:44:29 PM PDT 24
Finished Apr 25 12:44:31 PM PDT 24
Peak memory 194608 kb
Host smart-531b2768-0bf4-4c1b-9ce0-1a5beb37de34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009694445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.4009694445
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.4138445985
Short name T309
Test name
Test status
Simulation time 35026917 ps
CPU time 0.79 seconds
Started Apr 25 12:44:31 PM PDT 24
Finished Apr 25 12:44:33 PM PDT 24
Peak memory 196144 kb
Host smart-cdb03285-220b-492b-ad4f-46f96ee76159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138445985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.4138445985
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.213899812
Short name T58
Test name
Test status
Simulation time 838778694 ps
CPU time 10.94 seconds
Started Apr 25 12:44:21 PM PDT 24
Finished Apr 25 12:44:36 PM PDT 24
Peak memory 196732 kb
Host smart-0e90d801-b788-46c9-8d65-5e706a1e6766
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213899812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.213899812
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3274652093
Short name T232
Test name
Test status
Simulation time 265915953 ps
CPU time 1.01 seconds
Started Apr 25 12:44:14 PM PDT 24
Finished Apr 25 12:44:18 PM PDT 24
Peak memory 196704 kb
Host smart-72102776-bd34-4360-839d-5b78cc1907f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274652093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3274652093
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1677784839
Short name T433
Test name
Test status
Simulation time 73791292 ps
CPU time 1.08 seconds
Started Apr 25 12:44:15 PM PDT 24
Finished Apr 25 12:44:19 PM PDT 24
Peak memory 196004 kb
Host smart-c5ff7ad7-ca48-454d-9d4b-411779893e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677784839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1677784839
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1390963320
Short name T710
Test name
Test status
Simulation time 23941932 ps
CPU time 1.02 seconds
Started Apr 25 12:44:24 PM PDT 24
Finished Apr 25 12:44:29 PM PDT 24
Peak memory 196240 kb
Host smart-85253e6b-a4ea-4bd2-a762-880df66e3222
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390963320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1390963320
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.269052264
Short name T15
Test name
Test status
Simulation time 255688522 ps
CPU time 2.7 seconds
Started Apr 25 12:44:17 PM PDT 24
Finished Apr 25 12:44:23 PM PDT 24
Peak memory 198132 kb
Host smart-973fa0b4-fbad-4b79-9b21-b14e17d03e22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269052264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
269052264
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1391540295
Short name T312
Test name
Test status
Simulation time 80583549 ps
CPU time 0.94 seconds
Started Apr 25 12:44:21 PM PDT 24
Finished Apr 25 12:44:25 PM PDT 24
Peak memory 195960 kb
Host smart-ff8215ac-a8ce-42ef-a4ea-48ae29d4ab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391540295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1391540295
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1249713901
Short name T469
Test name
Test status
Simulation time 37340653 ps
CPU time 0.84 seconds
Started Apr 25 12:44:22 PM PDT 24
Finished Apr 25 12:44:26 PM PDT 24
Peak memory 196752 kb
Host smart-455b3594-5cee-40ed-b7ff-987b1959cc6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249713901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1249713901
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3900125389
Short name T593
Test name
Test status
Simulation time 237625692 ps
CPU time 2.76 seconds
Started Apr 25 12:44:30 PM PDT 24
Finished Apr 25 12:44:34 PM PDT 24
Peak memory 198060 kb
Host smart-2ddb9811-b1fc-4679-9c2b-3ad08492e3d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900125389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3900125389
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1671046724
Short name T624
Test name
Test status
Simulation time 125371386 ps
CPU time 1.28 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:44:12 PM PDT 24
Peak memory 195880 kb
Host smart-f967f3d6-8635-48a3-8ff3-1d1c7e61b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671046724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1671046724
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2363821506
Short name T654
Test name
Test status
Simulation time 102491125 ps
CPU time 0.92 seconds
Started Apr 25 12:44:20 PM PDT 24
Finished Apr 25 12:44:25 PM PDT 24
Peak memory 196440 kb
Host smart-89eb5da1-5feb-4289-b716-c1d97f566528
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363821506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2363821506
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.4048291317
Short name T720
Test name
Test status
Simulation time 13598600654 ps
CPU time 127.24 seconds
Started Apr 25 12:44:08 PM PDT 24
Finished Apr 25 12:46:19 PM PDT 24
Peak memory 198236 kb
Host smart-c4e0096a-02bb-47fe-af30-8ac9e1c1d045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048291317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.4048291317
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.213146238
Short name T486
Test name
Test status
Simulation time 30001956 ps
CPU time 0.58 seconds
Started Apr 25 12:44:20 PM PDT 24
Finished Apr 25 12:44:24 PM PDT 24
Peak memory 193936 kb
Host smart-d39be701-03fe-444d-929b-755e8fad4832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213146238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.213146238
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.320397219
Short name T492
Test name
Test status
Simulation time 32484971 ps
CPU time 0.75 seconds
Started Apr 25 12:44:30 PM PDT 24
Finished Apr 25 12:44:32 PM PDT 24
Peak memory 195316 kb
Host smart-33b657e8-c5c9-4c53-91b9-8859b87dc130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320397219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.320397219
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3284134893
Short name T533
Test name
Test status
Simulation time 2232970451 ps
CPU time 19.54 seconds
Started Apr 25 12:44:16 PM PDT 24
Finished Apr 25 12:44:38 PM PDT 24
Peak memory 197032 kb
Host smart-05348972-4dc6-46bc-be3b-e6d14f92e404
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284134893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3284134893
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1075298212
Short name T308
Test name
Test status
Simulation time 56999743 ps
CPU time 0.94 seconds
Started Apr 25 12:44:20 PM PDT 24
Finished Apr 25 12:44:24 PM PDT 24
Peak memory 197876 kb
Host smart-4074c254-0857-4c4e-a862-6ba1febafe14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075298212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1075298212
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3285403884
Short name T474
Test name
Test status
Simulation time 53769175 ps
CPU time 1.06 seconds
Started Apr 25 12:44:12 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 196060 kb
Host smart-6d7505bb-17e7-4d78-9075-61add447be9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285403884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3285403884
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2261975598
Short name T25
Test name
Test status
Simulation time 487432320 ps
CPU time 2.77 seconds
Started Apr 25 12:44:20 PM PDT 24
Finished Apr 25 12:44:26 PM PDT 24
Peak memory 198020 kb
Host smart-cbb20136-eb73-4000-97e2-1a3eed0a7723
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261975598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2261975598
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2022002556
Short name T459
Test name
Test status
Simulation time 284019064 ps
CPU time 2.62 seconds
Started Apr 25 12:44:16 PM PDT 24
Finished Apr 25 12:44:22 PM PDT 24
Peak memory 198012 kb
Host smart-7e9053d2-226f-4d89-a946-f38f1e269715
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022002556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2022002556
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2486862366
Short name T688
Test name
Test status
Simulation time 63648608 ps
CPU time 0.69 seconds
Started Apr 25 12:44:17 PM PDT 24
Finished Apr 25 12:44:21 PM PDT 24
Peak memory 195376 kb
Host smart-b500fc60-fd18-4144-acca-fa6f6d4d6d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486862366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2486862366
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.148645476
Short name T136
Test name
Test status
Simulation time 28313007 ps
CPU time 0.82 seconds
Started Apr 25 12:44:25 PM PDT 24
Finished Apr 25 12:44:28 PM PDT 24
Peak memory 196660 kb
Host smart-5d82ba51-6c6a-449e-929f-a2264a37cb61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148645476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.148645476
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.958706157
Short name T364
Test name
Test status
Simulation time 568612255 ps
CPU time 5.13 seconds
Started Apr 25 12:44:19 PM PDT 24
Finished Apr 25 12:44:27 PM PDT 24
Peak memory 197996 kb
Host smart-2c01fb96-8965-4324-b496-9cd381cda23a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958706157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.958706157
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2148429605
Short name T414
Test name
Test status
Simulation time 110106363 ps
CPU time 1.14 seconds
Started Apr 25 12:44:11 PM PDT 24
Finished Apr 25 12:44:16 PM PDT 24
Peak memory 196248 kb
Host smart-15a434ef-31d8-47a9-ba1f-7492755ed1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148429605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2148429605
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1017376296
Short name T236
Test name
Test status
Simulation time 48267928 ps
CPU time 1.05 seconds
Started Apr 25 12:44:10 PM PDT 24
Finished Apr 25 12:44:15 PM PDT 24
Peak memory 196536 kb
Host smart-17ef20d7-2285-47f7-9391-dcf7d470f434
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017376296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1017376296
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2666156793
Short name T234
Test name
Test status
Simulation time 66200039066 ps
CPU time 128.52 seconds
Started Apr 25 12:44:22 PM PDT 24
Finished Apr 25 12:46:33 PM PDT 24
Peak memory 198248 kb
Host smart-111f5b95-ebc2-4f72-bcb3-740dfdfc3abf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666156793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2666156793
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2691368625
Short name T33
Test name
Test status
Simulation time 21841785744 ps
CPU time 532.73 seconds
Started Apr 25 12:44:27 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 198320 kb
Host smart-c80a02e4-aae7-4cf8-8852-ad930e388a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2691368625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2691368625
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3074980317
Short name T124
Test name
Test status
Simulation time 13509156 ps
CPU time 0.56 seconds
Started Apr 25 12:44:24 PM PDT 24
Finished Apr 25 12:44:27 PM PDT 24
Peak memory 193936 kb
Host smart-0101379c-8e20-441b-a330-cc458d0f32b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074980317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3074980317
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.389162313
Short name T520
Test name
Test status
Simulation time 25998338 ps
CPU time 0.82 seconds
Started Apr 25 12:44:12 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 195416 kb
Host smart-7a58281e-4fc1-45e1-bba0-679592bca0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389162313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.389162313
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2884383609
Short name T620
Test name
Test status
Simulation time 234886057 ps
CPU time 6.63 seconds
Started Apr 25 12:44:26 PM PDT 24
Finished Apr 25 12:44:36 PM PDT 24
Peak memory 196920 kb
Host smart-55044f2b-60cf-40ee-9326-2403633b955b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884383609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2884383609
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1425634145
Short name T285
Test name
Test status
Simulation time 1072418355 ps
CPU time 1.03 seconds
Started Apr 25 12:44:24 PM PDT 24
Finished Apr 25 12:44:29 PM PDT 24
Peak memory 196612 kb
Host smart-a1979a08-a092-453c-a1e1-9d9e198db0a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425634145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1425634145
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.414968567
Short name T194
Test name
Test status
Simulation time 21823434 ps
CPU time 0.83 seconds
Started Apr 25 12:44:26 PM PDT 24
Finished Apr 25 12:44:30 PM PDT 24
Peak memory 196312 kb
Host smart-f968568c-b1f8-4416-9a6b-56af4d389750
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414968567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.414968567
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.638347436
Short name T268
Test name
Test status
Simulation time 54730619 ps
CPU time 1.32 seconds
Started Apr 25 12:44:17 PM PDT 24
Finished Apr 25 12:44:21 PM PDT 24
Peak memory 196736 kb
Host smart-4037b8f1-1a87-4bcf-87ab-5b6380b8c7d5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638347436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.638347436
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3292696065
Short name T185
Test name
Test status
Simulation time 308096405 ps
CPU time 1.95 seconds
Started Apr 25 12:44:20 PM PDT 24
Finished Apr 25 12:44:25 PM PDT 24
Peak memory 196172 kb
Host smart-fa8d369d-da37-4ecd-8941-af77b0356f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292696065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3292696065
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3065502596
Short name T198
Test name
Test status
Simulation time 34464721 ps
CPU time 0.86 seconds
Started Apr 25 12:44:21 PM PDT 24
Finished Apr 25 12:44:25 PM PDT 24
Peak memory 197204 kb
Host smart-77f5f288-3a8d-4cc8-a94a-c297e562db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065502596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3065502596
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.970376809
Short name T662
Test name
Test status
Simulation time 84983028 ps
CPU time 0.93 seconds
Started Apr 25 12:44:14 PM PDT 24
Finished Apr 25 12:44:18 PM PDT 24
Peak memory 196140 kb
Host smart-2cbf9815-4ba2-4ec3-83a0-70baf00ccab2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970376809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.970376809
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1260507477
Short name T21
Test name
Test status
Simulation time 246055913 ps
CPU time 3.13 seconds
Started Apr 25 12:44:20 PM PDT 24
Finished Apr 25 12:44:27 PM PDT 24
Peak memory 198036 kb
Host smart-87179294-47e3-4b04-ab1d-b9071f8471a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260507477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1260507477
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1002033776
Short name T77
Test name
Test status
Simulation time 31601151 ps
CPU time 0.75 seconds
Started Apr 25 12:44:26 PM PDT 24
Finished Apr 25 12:44:30 PM PDT 24
Peak memory 195880 kb
Host smart-ec90252f-88b1-41c1-9c99-27885b3c9b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002033776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1002033776
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3058785606
Short name T423
Test name
Test status
Simulation time 99505202 ps
CPU time 0.86 seconds
Started Apr 25 12:44:18 PM PDT 24
Finished Apr 25 12:44:22 PM PDT 24
Peak memory 196516 kb
Host smart-87df4a29-4624-401e-8955-669206512165
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058785606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3058785606
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.277915314
Short name T8
Test name
Test status
Simulation time 15597690815 ps
CPU time 169.44 seconds
Started Apr 25 12:44:22 PM PDT 24
Finished Apr 25 12:47:14 PM PDT 24
Peak memory 198256 kb
Host smart-6451b38d-da22-4858-bcbf-d1564471ab60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277915314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.277915314
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.115664615
Short name T673
Test name
Test status
Simulation time 50684114 ps
CPU time 0.58 seconds
Started Apr 25 12:44:22 PM PDT 24
Finished Apr 25 12:44:26 PM PDT 24
Peak memory 194076 kb
Host smart-7a7929a1-c1b0-45c1-a882-23138883a2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115664615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.115664615
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.950785593
Short name T507
Test name
Test status
Simulation time 189932688 ps
CPU time 0.91 seconds
Started Apr 25 12:44:23 PM PDT 24
Finished Apr 25 12:44:27 PM PDT 24
Peak memory 197304 kb
Host smart-5153f3d8-a209-4170-9937-094c2a7ff52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950785593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.950785593
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2231479594
Short name T208
Test name
Test status
Simulation time 6632372008 ps
CPU time 24.55 seconds
Started Apr 25 12:44:22 PM PDT 24
Finished Apr 25 12:44:50 PM PDT 24
Peak memory 198152 kb
Host smart-af4fb9b7-6d70-47a8-b679-597651394c4f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231479594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2231479594
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3011419323
Short name T380
Test name
Test status
Simulation time 50618321 ps
CPU time 0.83 seconds
Started Apr 25 12:44:21 PM PDT 24
Finished Apr 25 12:44:25 PM PDT 24
Peak memory 195984 kb
Host smart-06006794-338c-4384-86ae-08600aaedf22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011419323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3011419323
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.248925117
Short name T494
Test name
Test status
Simulation time 115733675 ps
CPU time 1.05 seconds
Started Apr 25 12:44:14 PM PDT 24
Finished Apr 25 12:44:18 PM PDT 24
Peak memory 196748 kb
Host smart-599a7f91-3e3b-4cf9-937a-99a57f8c4e01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248925117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.248925117
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1856518697
Short name T248
Test name
Test status
Simulation time 121372512 ps
CPU time 1.49 seconds
Started Apr 25 12:44:16 PM PDT 24
Finished Apr 25 12:44:20 PM PDT 24
Peak memory 197928 kb
Host smart-ba89d005-b434-434f-bdf0-55ec8221dcc3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856518697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1856518697
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2643844351
Short name T481
Test name
Test status
Simulation time 252787990 ps
CPU time 2.56 seconds
Started Apr 25 12:44:14 PM PDT 24
Finished Apr 25 12:44:20 PM PDT 24
Peak memory 197508 kb
Host smart-597a7212-7de8-4bc1-b4f0-25baa1911704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643844351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2643844351
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2406510470
Short name T239
Test name
Test status
Simulation time 131635717 ps
CPU time 0.76 seconds
Started Apr 25 12:44:25 PM PDT 24
Finished Apr 25 12:44:29 PM PDT 24
Peak memory 195396 kb
Host smart-a4bef24b-0d9c-4617-a42a-96e6552c21f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406510470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2406510470
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.245621110
Short name T407
Test name
Test status
Simulation time 48222957 ps
CPU time 1.08 seconds
Started Apr 25 12:44:17 PM PDT 24
Finished Apr 25 12:44:21 PM PDT 24
Peak memory 195972 kb
Host smart-0bb1d360-30b0-4463-96f8-d76503fd41c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245621110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.245621110
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.719427233
Short name T20
Test name
Test status
Simulation time 271849511 ps
CPU time 3.39 seconds
Started Apr 25 12:44:22 PM PDT 24
Finished Apr 25 12:44:29 PM PDT 24
Peak memory 198024 kb
Host smart-6e13a15e-d5ed-4716-95a1-34804eeb5193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719427233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.719427233
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.945832639
Short name T644
Test name
Test status
Simulation time 427761885 ps
CPU time 1.11 seconds
Started Apr 25 12:44:12 PM PDT 24
Finished Apr 25 12:44:17 PM PDT 24
Peak memory 195580 kb
Host smart-59a57e47-fa0c-47f4-84bb-477aa7baa638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945832639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.945832639
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2883024526
Short name T580
Test name
Test status
Simulation time 353210786 ps
CPU time 1.53 seconds
Started Apr 25 12:44:26 PM PDT 24
Finished Apr 25 12:44:30 PM PDT 24
Peak memory 198008 kb
Host smart-e2852c94-bb1c-40e2-9501-c5e37c74906b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883024526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2883024526
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3136026681
Short name T346
Test name
Test status
Simulation time 30812012262 ps
CPU time 42.11 seconds
Started Apr 25 12:44:19 PM PDT 24
Finished Apr 25 12:45:05 PM PDT 24
Peak memory 198252 kb
Host smart-bb145e15-af65-473c-868e-6f36d9169ea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136026681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3136026681
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2857113501
Short name T417
Test name
Test status
Simulation time 47909669 ps
CPU time 0.57 seconds
Started Apr 25 12:44:28 PM PDT 24
Finished Apr 25 12:44:31 PM PDT 24
Peak memory 193916 kb
Host smart-cc8b0f4e-fd00-4dd6-94dc-4b5ed3c78990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857113501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2857113501
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.125855145
Short name T586
Test name
Test status
Simulation time 178824015 ps
CPU time 0.85 seconds
Started Apr 25 12:44:19 PM PDT 24
Finished Apr 25 12:44:23 PM PDT 24
Peak memory 196516 kb
Host smart-c78c8124-a25c-4b91-b5ec-a27b46f34c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125855145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.125855145
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2193325096
Short name T460
Test name
Test status
Simulation time 1642035610 ps
CPU time 12.47 seconds
Started Apr 25 12:44:24 PM PDT 24
Finished Apr 25 12:44:40 PM PDT 24
Peak memory 197960 kb
Host smart-131fea61-1459-434d-a28a-9d9b13ae2241
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193325096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2193325096
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3410758271
Short name T182
Test name
Test status
Simulation time 384513364 ps
CPU time 1.01 seconds
Started Apr 25 12:44:25 PM PDT 24
Finished Apr 25 12:44:29 PM PDT 24
Peak memory 196452 kb
Host smart-91d6c793-665a-458e-87f0-6b116930125a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410758271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3410758271
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2747662704
Short name T167
Test name
Test status
Simulation time 186138425 ps
CPU time 1.38 seconds
Started Apr 25 12:44:20 PM PDT 24
Finished Apr 25 12:44:25 PM PDT 24
Peak memory 195852 kb
Host smart-16299a2b-1efb-40a1-a17a-e17f5a01e132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747662704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2747662704
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.73526259
Short name T443
Test name
Test status
Simulation time 1128803636 ps
CPU time 2.8 seconds
Started Apr 25 12:44:22 PM PDT 24
Finished Apr 25 12:44:28 PM PDT 24
Peak memory 196324 kb
Host smart-6eaac31a-172f-4c70-abc1-f2584c3e4249
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73526259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.gpio_intr_with_filter_rand_intr_event.73526259
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2332191988
Short name T216
Test name
Test status
Simulation time 79758860 ps
CPU time 1.35 seconds
Started Apr 25 12:44:19 PM PDT 24
Finished Apr 25 12:44:23 PM PDT 24
Peak memory 196108 kb
Host smart-1b2aa0c3-3d88-46cf-b808-fa65c2e0cbf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332191988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2332191988
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2755179340
Short name T574
Test name
Test status
Simulation time 29255891 ps
CPU time 0.76 seconds
Started Apr 25 12:44:18 PM PDT 24
Finished Apr 25 12:44:21 PM PDT 24
Peak memory 196268 kb
Host smart-ea3151c7-448e-42ad-a525-250830217f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755179340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2755179340
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2076766339
Short name T428
Test name
Test status
Simulation time 231240629 ps
CPU time 1 seconds
Started Apr 25 12:44:28 PM PDT 24
Finished Apr 25 12:44:31 PM PDT 24
Peak memory 195928 kb
Host smart-ab9c4d90-c734-488d-9467-acc94b45b4a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076766339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2076766339
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2223520836
Short name T430
Test name
Test status
Simulation time 330972411 ps
CPU time 3.75 seconds
Started Apr 25 12:44:33 PM PDT 24
Finished Apr 25 12:44:37 PM PDT 24
Peak memory 198076 kb
Host smart-1487ff17-6909-4898-8700-6f367388f210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223520836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2223520836
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.127273445
Short name T126
Test name
Test status
Simulation time 51201852 ps
CPU time 1.03 seconds
Started Apr 25 12:44:18 PM PDT 24
Finished Apr 25 12:44:22 PM PDT 24
Peak memory 195604 kb
Host smart-cd7273b8-7ed6-427c-b12a-5783b74e3824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127273445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.127273445
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3443745034
Short name T512
Test name
Test status
Simulation time 45001973 ps
CPU time 0.74 seconds
Started Apr 25 12:44:15 PM PDT 24
Finished Apr 25 12:44:19 PM PDT 24
Peak memory 194972 kb
Host smart-8e149661-464d-4806-912b-b725876d7527
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443745034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3443745034
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3538241968
Short name T648
Test name
Test status
Simulation time 8261041955 ps
CPU time 90.77 seconds
Started Apr 25 12:44:15 PM PDT 24
Finished Apr 25 12:45:49 PM PDT 24
Peak memory 198208 kb
Host smart-66d6cfa8-9163-4375-8b89-ebe18bfdda33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538241968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3538241968
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.525377645
Short name T431
Test name
Test status
Simulation time 21381079 ps
CPU time 0.6 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:57 PM PDT 24
Peak memory 193920 kb
Host smart-36bb65dd-1e08-486a-a809-91f1bdd4865d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525377645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.525377645
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2766942616
Short name T118
Test name
Test status
Simulation time 90705418 ps
CPU time 0.73 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 194192 kb
Host smart-3938692a-88e2-4644-a183-a09c82cc6576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766942616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2766942616
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4182167580
Short name T532
Test name
Test status
Simulation time 504479755 ps
CPU time 26.28 seconds
Started Apr 25 12:42:50 PM PDT 24
Finished Apr 25 12:43:20 PM PDT 24
Peak memory 197956 kb
Host smart-f667bf7a-be18-4222-8791-b393822cdf45
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182167580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4182167580
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.443055167
Short name T540
Test name
Test status
Simulation time 127678731 ps
CPU time 0.65 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 194552 kb
Host smart-a970afaf-5fd5-4a39-a3db-7dda9f1edb3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443055167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.443055167
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3991605490
Short name T718
Test name
Test status
Simulation time 139831822 ps
CPU time 1.12 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:57 PM PDT 24
Peak memory 196200 kb
Host smart-85a94892-0a79-4268-9527-908c9b3f6055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991605490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3991605490
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2666624913
Short name T483
Test name
Test status
Simulation time 145593587 ps
CPU time 3 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 198092 kb
Host smart-6e03ce60-213b-420f-a845-d82865389ae4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666624913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2666624913
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1076423671
Short name T60
Test name
Test status
Simulation time 298094834 ps
CPU time 3.24 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:43:00 PM PDT 24
Peak memory 195780 kb
Host smart-ad1f9fef-3ca1-4102-bfff-cec312c69fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076423671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1076423671
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.47229098
Short name T252
Test name
Test status
Simulation time 92484847 ps
CPU time 0.99 seconds
Started Apr 25 12:42:49 PM PDT 24
Finished Apr 25 12:42:53 PM PDT 24
Peak memory 195992 kb
Host smart-9ccc308f-5544-4f42-9178-c45e5960bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47229098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.47229098
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3031278611
Short name T415
Test name
Test status
Simulation time 36861448 ps
CPU time 0.98 seconds
Started Apr 25 12:42:50 PM PDT 24
Finished Apr 25 12:42:55 PM PDT 24
Peak memory 196080 kb
Host smart-f1b59954-7153-49dd-86bf-6a485ed56699
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031278611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3031278611
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.278835278
Short name T701
Test name
Test status
Simulation time 303973813 ps
CPU time 1.28 seconds
Started Apr 25 12:42:54 PM PDT 24
Finished Apr 25 12:43:00 PM PDT 24
Peak memory 197928 kb
Host smart-5d7892c3-b31a-4adf-b099-054d5efd1e3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278835278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.278835278
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3037198056
Short name T420
Test name
Test status
Simulation time 71381733 ps
CPU time 1.08 seconds
Started Apr 25 12:42:57 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 195512 kb
Host smart-b9c1117a-a0b9-4e19-8a88-2f61f8beeb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037198056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3037198056
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.115652297
Short name T135
Test name
Test status
Simulation time 53793602 ps
CPU time 0.97 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 195576 kb
Host smart-bd61edbb-ec17-4d09-9665-929ff225d4a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115652297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.115652297
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2096558083
Short name T487
Test name
Test status
Simulation time 20745478192 ps
CPU time 145.11 seconds
Started Apr 25 12:42:54 PM PDT 24
Finished Apr 25 12:45:23 PM PDT 24
Peak memory 198132 kb
Host smart-fadf501a-89ad-4b83-9b46-fc24c5bf3ac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096558083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2096558083
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1476362640
Short name T71
Test name
Test status
Simulation time 100190119111 ps
CPU time 2231.32 seconds
Started Apr 25 12:42:51 PM PDT 24
Finished Apr 25 01:20:09 PM PDT 24
Peak memory 198260 kb
Host smart-704a3d35-f1da-4200-974c-6e6a9a4bb6c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1476362640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1476362640
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3572958964
Short name T162
Test name
Test status
Simulation time 36341387 ps
CPU time 0.55 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:42:57 PM PDT 24
Peak memory 194196 kb
Host smart-1ab6212f-faf0-48aa-b9ce-95bb4638458e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572958964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3572958964
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2365784643
Short name T583
Test name
Test status
Simulation time 148353974 ps
CPU time 0.87 seconds
Started Apr 25 12:42:50 PM PDT 24
Finished Apr 25 12:42:54 PM PDT 24
Peak memory 197268 kb
Host smart-54381280-10af-4db4-bfcd-c497f3ba3fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365784643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2365784643
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2668515123
Short name T650
Test name
Test status
Simulation time 1142605663 ps
CPU time 11.61 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:43:07 PM PDT 24
Peak memory 195588 kb
Host smart-ec4a2556-8b6a-405f-81a4-3d99c00a70ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668515123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2668515123
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1905756310
Short name T335
Test name
Test status
Simulation time 265141416 ps
CPU time 0.94 seconds
Started Apr 25 12:42:55 PM PDT 24
Finished Apr 25 12:43:00 PM PDT 24
Peak memory 197788 kb
Host smart-8463924f-17c5-4848-9304-b46e90e49f18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905756310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1905756310
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1436946149
Short name T591
Test name
Test status
Simulation time 37299362 ps
CPU time 0.99 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:57 PM PDT 24
Peak memory 196036 kb
Host smart-076cc72f-eb09-4502-b902-a823f8d5c12e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436946149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1436946149
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.693526452
Short name T721
Test name
Test status
Simulation time 368282486 ps
CPU time 3.67 seconds
Started Apr 25 12:42:50 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 198080 kb
Host smart-e08b75d2-8323-4d42-8dc4-ba56a8c410dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693526452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.693526452
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2256317305
Short name T217
Test name
Test status
Simulation time 111605221 ps
CPU time 2.43 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 196580 kb
Host smart-c5d8c25a-7007-4e2c-a02f-c6fda25c1837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256317305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2256317305
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3385600552
Short name T377
Test name
Test status
Simulation time 61276983 ps
CPU time 0.68 seconds
Started Apr 25 12:42:50 PM PDT 24
Finished Apr 25 12:42:54 PM PDT 24
Peak memory 194328 kb
Host smart-45026b72-cdc4-41c7-a1d2-facb1296ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385600552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3385600552
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.344231605
Short name T499
Test name
Test status
Simulation time 211982675 ps
CPU time 1.19 seconds
Started Apr 25 12:43:14 PM PDT 24
Finished Apr 25 12:43:18 PM PDT 24
Peak memory 198064 kb
Host smart-f0a706f3-a908-40d4-83b5-e92f9e7dc5d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344231605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.344231605
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.301150731
Short name T139
Test name
Test status
Simulation time 30951592 ps
CPU time 1.38 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 197956 kb
Host smart-1181f8a0-9585-4de5-b029-3145cb1b065e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301150731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.301150731
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.837993216
Short name T350
Test name
Test status
Simulation time 50740628 ps
CPU time 0.74 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:57 PM PDT 24
Peak memory 195232 kb
Host smart-e6bdc130-d84b-4bb2-bd15-580854e8a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837993216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.837993216
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2359043675
Short name T617
Test name
Test status
Simulation time 79686506 ps
CPU time 0.99 seconds
Started Apr 25 12:42:55 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 195712 kb
Host smart-1a2918f6-8384-486b-947a-8ccc2819af53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359043675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2359043675
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.840279928
Short name T626
Test name
Test status
Simulation time 35427117710 ps
CPU time 209.07 seconds
Started Apr 25 12:42:58 PM PDT 24
Finished Apr 25 12:46:29 PM PDT 24
Peak memory 198176 kb
Host smart-485f5cd7-8c4c-4080-8300-c075a051dc0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840279928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.840279928
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.810093340
Short name T70
Test name
Test status
Simulation time 118126590947 ps
CPU time 718.89 seconds
Started Apr 25 12:42:51 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 198228 kb
Host smart-b20c5cdb-8020-4c58-bd99-0ead25b0b8a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=810093340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.810093340
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2004706418
Short name T130
Test name
Test status
Simulation time 12272441 ps
CPU time 0.57 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 194000 kb
Host smart-0c927dce-6c10-45cf-9682-a4920ecf6dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004706418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2004706418
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1850215299
Short name T490
Test name
Test status
Simulation time 38826585 ps
CPU time 0.76 seconds
Started Apr 25 12:42:54 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 195312 kb
Host smart-1d44cbd5-391b-4422-9da2-b40b94de217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850215299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1850215299
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1474176304
Short name T26
Test name
Test status
Simulation time 3740903252 ps
CPU time 9.29 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:43:07 PM PDT 24
Peak memory 198176 kb
Host smart-cf7a8f25-a3bc-4739-9a6a-d616f9d95157
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474176304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1474176304
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1604791111
Short name T186
Test name
Test status
Simulation time 57444299 ps
CPU time 0.96 seconds
Started Apr 25 12:42:57 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 196952 kb
Host smart-55254d4e-0910-4cea-a189-366683cd68b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604791111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1604791111
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3060706866
Short name T696
Test name
Test status
Simulation time 40653156 ps
CPU time 1.2 seconds
Started Apr 25 12:42:57 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 196820 kb
Host smart-06cc0755-ed12-4a60-9446-9f6112344916
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060706866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3060706866
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.951440023
Short name T181
Test name
Test status
Simulation time 266430617 ps
CPU time 1.36 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 196528 kb
Host smart-2171fb15-c354-4c59-971f-aaf711e48450
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951440023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.951440023
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4210432770
Short name T128
Test name
Test status
Simulation time 692360024 ps
CPU time 1.41 seconds
Started Apr 25 12:42:57 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 196528 kb
Host smart-d6b6022a-9eae-4d3a-ad5a-ba60ee4b65ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210432770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
4210432770
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1311764255
Short name T143
Test name
Test status
Simulation time 50671091 ps
CPU time 1.21 seconds
Started Apr 25 12:42:54 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 196748 kb
Host smart-c537da26-c372-4ea1-b983-ca7f88145455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311764255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1311764255
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3055637621
Short name T176
Test name
Test status
Simulation time 35226535 ps
CPU time 0.65 seconds
Started Apr 25 12:42:51 PM PDT 24
Finished Apr 25 12:42:56 PM PDT 24
Peak memory 194280 kb
Host smart-2e335c24-1f89-45f2-a8b8-c317d4b09ee8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055637621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3055637621
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2516212608
Short name T323
Test name
Test status
Simulation time 50692509 ps
CPU time 2.1 seconds
Started Apr 25 12:42:49 PM PDT 24
Finished Apr 25 12:42:53 PM PDT 24
Peak memory 197852 kb
Host smart-3e26d08e-9e2e-4dc2-aed0-d3acca25c812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516212608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2516212608
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3860773314
Short name T357
Test name
Test status
Simulation time 217147528 ps
CPU time 1.28 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 196816 kb
Host smart-193d47a0-c5be-4ee4-8d06-da13ee0a99ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860773314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3860773314
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.358704874
Short name T604
Test name
Test status
Simulation time 139933232 ps
CPU time 1.23 seconds
Started Apr 25 12:42:58 PM PDT 24
Finished Apr 25 12:43:02 PM PDT 24
Peak memory 196696 kb
Host smart-b4dd03fd-dfe1-4990-a386-34f7c95f16db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358704874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.358704874
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2129679759
Short name T578
Test name
Test status
Simulation time 78827934023 ps
CPU time 192.09 seconds
Started Apr 25 12:42:54 PM PDT 24
Finished Apr 25 12:46:10 PM PDT 24
Peak memory 198176 kb
Host smart-a2225496-0e82-41e6-8953-1208b2494ae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129679759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2129679759
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.508870434
Short name T255
Test name
Test status
Simulation time 49215921 ps
CPU time 0.62 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:03 PM PDT 24
Peak memory 193992 kb
Host smart-37458ad2-fb7c-48f5-8cfb-d5052f85b6fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508870434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.508870434
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4264301480
Short name T564
Test name
Test status
Simulation time 96465429 ps
CPU time 0.87 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:57 PM PDT 24
Peak memory 196424 kb
Host smart-5a351651-9221-481c-9276-ad40ecb82f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264301480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4264301480
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.753600858
Short name T368
Test name
Test status
Simulation time 502873213 ps
CPU time 13.43 seconds
Started Apr 25 12:42:54 PM PDT 24
Finished Apr 25 12:43:11 PM PDT 24
Peak memory 196228 kb
Host smart-92febaf2-9306-44c4-adca-4a1bc4f8ebe6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753600858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.753600858
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1989081739
Short name T589
Test name
Test status
Simulation time 43463651 ps
CPU time 0.72 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:57 PM PDT 24
Peak memory 194888 kb
Host smart-b1d097ff-2834-460b-af99-a3f6e81de02f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989081739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1989081739
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2704041564
Short name T269
Test name
Test status
Simulation time 141046928 ps
CPU time 1.45 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 197120 kb
Host smart-80922973-7264-4db7-88b9-a8531492307b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704041564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2704041564
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.48973965
Short name T376
Test name
Test status
Simulation time 32888796 ps
CPU time 1.38 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 198084 kb
Host smart-e832fa9f-060e-4bda-a3cc-636e8a661825
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48973965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.gpio_intr_with_filter_rand_intr_event.48973965
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2897026003
Short name T352
Test name
Test status
Simulation time 105954677 ps
CPU time 3.12 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 196492 kb
Host smart-e3e3a29f-4ed2-43aa-a14b-00f5a5df21d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897026003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2897026003
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3747132956
Short name T454
Test name
Test status
Simulation time 20716082 ps
CPU time 0.74 seconds
Started Apr 25 12:42:57 PM PDT 24
Finished Apr 25 12:43:00 PM PDT 24
Peak memory 195476 kb
Host smart-b31ea058-fa11-4606-a135-e327910a8e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747132956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3747132956
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2623139353
Short name T421
Test name
Test status
Simulation time 92085438 ps
CPU time 1.07 seconds
Started Apr 25 12:42:57 PM PDT 24
Finished Apr 25 12:43:01 PM PDT 24
Peak memory 195996 kb
Host smart-c8182718-8e78-4926-a717-fffb9fb4cdd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623139353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2623139353
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1645813407
Short name T638
Test name
Test status
Simulation time 401260373 ps
CPU time 5.48 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:43:03 PM PDT 24
Peak memory 197900 kb
Host smart-997b213e-344f-4613-b02d-ee4ff389b96f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645813407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1645813407
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3517549206
Short name T509
Test name
Test status
Simulation time 291003768 ps
CPU time 1.24 seconds
Started Apr 25 12:42:51 PM PDT 24
Finished Apr 25 12:42:56 PM PDT 24
Peak memory 196560 kb
Host smart-c26476ae-5477-4c0a-9d0a-332e2138e898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517549206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3517549206
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3415060410
Short name T200
Test name
Test status
Simulation time 67110964 ps
CPU time 1.32 seconds
Started Apr 25 12:42:52 PM PDT 24
Finished Apr 25 12:42:58 PM PDT 24
Peak memory 196932 kb
Host smart-f8408e27-37ef-4320-ade9-c91cf298df33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415060410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3415060410
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.178847743
Short name T258
Test name
Test status
Simulation time 8574900568 ps
CPU time 111.57 seconds
Started Apr 25 12:42:53 PM PDT 24
Finished Apr 25 12:44:49 PM PDT 24
Peak memory 198200 kb
Host smart-c82ea36c-242b-43c8-a7f7-f0ed0bf5f7c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178847743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.178847743
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3483089366
Short name T613
Test name
Test status
Simulation time 37863128 ps
CPU time 0.62 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:16 PM PDT 24
Peak memory 194156 kb
Host smart-94003035-0818-431e-8331-12a5861a1839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483089366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3483089366
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3128364779
Short name T245
Test name
Test status
Simulation time 65298130 ps
CPU time 0.77 seconds
Started Apr 25 12:42:59 PM PDT 24
Finished Apr 25 12:43:02 PM PDT 24
Peak memory 195280 kb
Host smart-f52e6f99-48ef-4e54-9237-2cb253ddc988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128364779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3128364779
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1176002146
Short name T161
Test name
Test status
Simulation time 625159397 ps
CPU time 10.55 seconds
Started Apr 25 12:43:14 PM PDT 24
Finished Apr 25 12:43:28 PM PDT 24
Peak memory 196896 kb
Host smart-d03ade68-2f42-4865-b1a6-913b7994bd67
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176002146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1176002146
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3894277051
Short name T706
Test name
Test status
Simulation time 106526715 ps
CPU time 0.85 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 196168 kb
Host smart-97b363fa-dc73-456f-857b-eec72d32d153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894277051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3894277051
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.650449745
Short name T144
Test name
Test status
Simulation time 432668205 ps
CPU time 1.09 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:04 PM PDT 24
Peak memory 196616 kb
Host smart-1fcbcf1c-c5bf-44aa-ab13-8b4f83dcf1ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650449745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.650449745
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1873883991
Short name T159
Test name
Test status
Simulation time 57585424 ps
CPU time 2.35 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 198096 kb
Host smart-6f7827d9-7f78-4f76-8311-e3df5d8886c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873883991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1873883991
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3197109640
Short name T310
Test name
Test status
Simulation time 199899439 ps
CPU time 2.93 seconds
Started Apr 25 12:43:02 PM PDT 24
Finished Apr 25 12:43:08 PM PDT 24
Peak memory 197000 kb
Host smart-ffa0abc9-cd9f-4453-bf5e-bd83b028decb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197109640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3197109640
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1681272045
Short name T558
Test name
Test status
Simulation time 206084181 ps
CPU time 1.1 seconds
Started Apr 25 12:43:02 PM PDT 24
Finished Apr 25 12:43:07 PM PDT 24
Peak memory 196608 kb
Host smart-da4e1532-d0ba-4914-b134-95d9884d6e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681272045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1681272045
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1069056535
Short name T278
Test name
Test status
Simulation time 59881292 ps
CPU time 0.74 seconds
Started Apr 25 12:43:00 PM PDT 24
Finished Apr 25 12:43:03 PM PDT 24
Peak memory 196164 kb
Host smart-d96d8bbc-347f-48c7-87d0-ab6cf511ba94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069056535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1069056535
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1449827141
Short name T556
Test name
Test status
Simulation time 409064162 ps
CPU time 4.69 seconds
Started Apr 25 12:42:59 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 197924 kb
Host smart-35710748-30ce-45c8-93be-72545de9dd38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449827141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1449827141
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3563875914
Short name T227
Test name
Test status
Simulation time 31019541 ps
CPU time 0.95 seconds
Started Apr 25 12:43:11 PM PDT 24
Finished Apr 25 12:43:16 PM PDT 24
Peak memory 196388 kb
Host smart-90ef834d-22eb-4115-8652-294b0ac060e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563875914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3563875914
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2073048771
Short name T78
Test name
Test status
Simulation time 94802648 ps
CPU time 0.75 seconds
Started Apr 25 12:43:01 PM PDT 24
Finished Apr 25 12:43:05 PM PDT 24
Peak memory 194996 kb
Host smart-2994353b-a81c-494c-8098-ccf6e90f4cfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073048771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2073048771
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2140216810
Short name T413
Test name
Test status
Simulation time 8423643680 ps
CPU time 111.62 seconds
Started Apr 25 12:43:03 PM PDT 24
Finished Apr 25 12:44:58 PM PDT 24
Peak memory 198180 kb
Host smart-499278ab-0c3e-4339-87e3-62e295c9832a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140216810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2140216810
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3205157014
Short name T901
Test name
Test status
Simulation time 116866681 ps
CPU time 1.22 seconds
Started Apr 25 12:32:05 PM PDT 24
Finished Apr 25 12:32:07 PM PDT 24
Peak memory 196876 kb
Host smart-cd7e749a-58d5-4af3-ac0d-26609046aada
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3205157014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3205157014
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4242400645
Short name T851
Test name
Test status
Simulation time 137522120 ps
CPU time 1.07 seconds
Started Apr 25 12:32:06 PM PDT 24
Finished Apr 25 12:32:08 PM PDT 24
Peak memory 198064 kb
Host smart-d8e6f18b-1117-41e5-aff0-9d3314d01a6f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242400645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4242400645
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.271490406
Short name T889
Test name
Test status
Simulation time 205528520 ps
CPU time 0.81 seconds
Started Apr 25 12:32:04 PM PDT 24
Finished Apr 25 12:32:06 PM PDT 24
Peak memory 196296 kb
Host smart-96a91dab-2ca9-42e3-8341-0e050d64c3dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=271490406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.271490406
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1978160698
Short name T930
Test name
Test status
Simulation time 247274911 ps
CPU time 1.28 seconds
Started Apr 25 12:32:05 PM PDT 24
Finished Apr 25 12:32:07 PM PDT 24
Peak memory 196608 kb
Host smart-2bb38306-b580-4efd-b4b2-d8a9cb08326b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978160698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1978160698
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1022350218
Short name T888
Test name
Test status
Simulation time 84397127 ps
CPU time 1.24 seconds
Started Apr 25 12:32:10 PM PDT 24
Finished Apr 25 12:32:13 PM PDT 24
Peak memory 196636 kb
Host smart-ffdd3154-9294-4626-b2f0-a2619859bb89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1022350218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1022350218
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1214392679
Short name T916
Test name
Test status
Simulation time 130595852 ps
CPU time 0.89 seconds
Started Apr 25 12:32:13 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 195676 kb
Host smart-ea209944-5eb6-43bd-a199-d851bee64ead
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214392679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1214392679
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3272141246
Short name T909
Test name
Test status
Simulation time 100033196 ps
CPU time 0.87 seconds
Started Apr 25 12:32:12 PM PDT 24
Finished Apr 25 12:32:14 PM PDT 24
Peak memory 195480 kb
Host smart-6dc0d821-92e1-4bf0-a334-5eac734d12c1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3272141246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3272141246
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1179884890
Short name T905
Test name
Test status
Simulation time 30287848 ps
CPU time 0.96 seconds
Started Apr 25 12:32:16 PM PDT 24
Finished Apr 25 12:32:18 PM PDT 24
Peak memory 195588 kb
Host smart-b105d44e-6c7e-43d3-ab64-1f6bec4bcb81
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179884890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1179884890
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.541094584
Short name T882
Test name
Test status
Simulation time 73036023 ps
CPU time 0.88 seconds
Started Apr 25 12:32:17 PM PDT 24
Finished Apr 25 12:32:18 PM PDT 24
Peak memory 197412 kb
Host smart-e7c5b00c-0190-4b86-9640-32a995a718da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=541094584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.541094584
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3732507482
Short name T937
Test name
Test status
Simulation time 43765498 ps
CPU time 1.22 seconds
Started Apr 25 12:32:15 PM PDT 24
Finished Apr 25 12:32:17 PM PDT 24
Peak memory 196808 kb
Host smart-cec5d571-d465-4658-9519-238c229178e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732507482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3732507482
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4232914226
Short name T897
Test name
Test status
Simulation time 38306733 ps
CPU time 1.13 seconds
Started Apr 25 12:32:13 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 198024 kb
Host smart-a28a74f6-452c-4057-b9dc-5a61b6dc67e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4232914226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.4232914226
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3425460458
Short name T944
Test name
Test status
Simulation time 236984662 ps
CPU time 0.93 seconds
Started Apr 25 12:32:10 PM PDT 24
Finished Apr 25 12:32:12 PM PDT 24
Peak memory 197376 kb
Host smart-c5ecc751-3da3-4f74-8f6e-baf65be42292
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425460458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3425460458
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1028809015
Short name T907
Test name
Test status
Simulation time 124789467 ps
CPU time 1.11 seconds
Started Apr 25 12:32:13 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 196512 kb
Host smart-641c9c9c-dd05-4fb8-a1c5-02c8ff1ea428
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1028809015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1028809015
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2388303303
Short name T947
Test name
Test status
Simulation time 64905643 ps
CPU time 0.95 seconds
Started Apr 25 12:32:14 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 196624 kb
Host smart-6c9d8b90-9fa5-433e-a143-8d38d29a2e2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388303303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2388303303
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1701215888
Short name T852
Test name
Test status
Simulation time 221996638 ps
CPU time 0.77 seconds
Started Apr 25 12:32:13 PM PDT 24
Finished Apr 25 12:32:15 PM PDT 24
Peak memory 195560 kb
Host smart-ddfe0a0a-f390-4d1d-9c24-b967e53b1667
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1701215888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1701215888
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513617751
Short name T875
Test name
Test status
Simulation time 207440423 ps
CPU time 1.26 seconds
Started Apr 25 12:32:13 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 196808 kb
Host smart-11085240-65c3-405c-a1ec-93b4384e8052
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513617751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.513617751
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2758611626
Short name T918
Test name
Test status
Simulation time 1154389999 ps
CPU time 1.26 seconds
Started Apr 25 12:32:12 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 196580 kb
Host smart-9f862f25-f9f9-4ad3-9e6c-db4cfa947037
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2758611626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2758611626
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.682359029
Short name T900
Test name
Test status
Simulation time 186183663 ps
CPU time 0.98 seconds
Started Apr 25 12:32:17 PM PDT 24
Finished Apr 25 12:32:19 PM PDT 24
Peak memory 195692 kb
Host smart-39e82cbe-2571-4aa0-9e75-a327ce21fcc2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682359029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.682359029
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3324114560
Short name T906
Test name
Test status
Simulation time 60161463 ps
CPU time 1.09 seconds
Started Apr 25 12:32:11 PM PDT 24
Finished Apr 25 12:32:14 PM PDT 24
Peak memory 196584 kb
Host smart-87972c08-8d46-4a30-85d4-0eca233c8f25
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3324114560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3324114560
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.353025953
Short name T942
Test name
Test status
Simulation time 179374541 ps
CPU time 1.08 seconds
Started Apr 25 12:32:12 PM PDT 24
Finished Apr 25 12:32:15 PM PDT 24
Peak memory 197632 kb
Host smart-2c4163ab-4bb8-4f15-9b89-70bc917a677a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353025953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.353025953
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1286737395
Short name T914
Test name
Test status
Simulation time 60390070 ps
CPU time 1.23 seconds
Started Apr 25 12:32:11 PM PDT 24
Finished Apr 25 12:32:13 PM PDT 24
Peak memory 195872 kb
Host smart-2803d90b-8232-488c-b19d-560e142138d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1286737395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1286737395
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3545409260
Short name T934
Test name
Test status
Simulation time 172874887 ps
CPU time 1.11 seconds
Started Apr 25 12:32:16 PM PDT 24
Finished Apr 25 12:32:18 PM PDT 24
Peak memory 196616 kb
Host smart-7baa2873-6211-401e-b234-554c92aa85d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545409260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3545409260
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2867867786
Short name T872
Test name
Test status
Simulation time 163390755 ps
CPU time 1.23 seconds
Started Apr 25 12:32:18 PM PDT 24
Finished Apr 25 12:32:21 PM PDT 24
Peak memory 196392 kb
Host smart-b0c927bb-e640-40b9-8685-2809314bd5db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2867867786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2867867786
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3281779300
Short name T935
Test name
Test status
Simulation time 56993673 ps
CPU time 0.77 seconds
Started Apr 25 12:32:11 PM PDT 24
Finished Apr 25 12:32:14 PM PDT 24
Peak memory 196224 kb
Host smart-9828d092-f8d6-40c6-8a13-77e6338cc0da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281779300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3281779300
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3465937948
Short name T859
Test name
Test status
Simulation time 161752686 ps
CPU time 1.47 seconds
Started Apr 25 12:32:04 PM PDT 24
Finished Apr 25 12:32:06 PM PDT 24
Peak memory 198004 kb
Host smart-6f7c3893-79c9-4c67-af23-81e4ff609c21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3465937948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3465937948
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.294784281
Short name T921
Test name
Test status
Simulation time 987715644 ps
CPU time 1.13 seconds
Started Apr 25 12:32:07 PM PDT 24
Finished Apr 25 12:32:09 PM PDT 24
Peak memory 198028 kb
Host smart-488d9892-fe25-43c1-8862-377caf21b23e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294784281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.294784281
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.120678149
Short name T932
Test name
Test status
Simulation time 37433388 ps
CPU time 0.99 seconds
Started Apr 25 12:32:14 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 196632 kb
Host smart-51c761fe-f612-42ae-b596-ac46f595c509
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=120678149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.120678149
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1497842444
Short name T922
Test name
Test status
Simulation time 577396910 ps
CPU time 1.27 seconds
Started Apr 25 12:32:17 PM PDT 24
Finished Apr 25 12:32:19 PM PDT 24
Peak memory 198056 kb
Host smart-5cc917bd-adeb-492a-b171-77780a7b7c42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497842444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1497842444
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1393269657
Short name T878
Test name
Test status
Simulation time 343901084 ps
CPU time 1.36 seconds
Started Apr 25 12:32:13 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 196648 kb
Host smart-bff6442d-3b30-457a-9bd7-fef6d74f1258
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1393269657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1393269657
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3567304902
Short name T923
Test name
Test status
Simulation time 102284556 ps
CPU time 1 seconds
Started Apr 25 12:32:11 PM PDT 24
Finished Apr 25 12:32:14 PM PDT 24
Peak memory 196548 kb
Host smart-e5aca7a7-e389-40d4-863f-0fb19f1d21a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567304902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3567304902
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1608331629
Short name T883
Test name
Test status
Simulation time 94988948 ps
CPU time 1.45 seconds
Started Apr 25 12:32:19 PM PDT 24
Finished Apr 25 12:32:21 PM PDT 24
Peak memory 196768 kb
Host smart-282aeea7-338b-49d8-8803-2a8f85434bd1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1608331629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1608331629
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054113135
Short name T848
Test name
Test status
Simulation time 163602579 ps
CPU time 0.94 seconds
Started Apr 25 12:33:29 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 195272 kb
Host smart-173ca6cd-f5f8-450b-96d0-9cdd9e7442c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054113135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4054113135
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.650835593
Short name T912
Test name
Test status
Simulation time 166135648 ps
CPU time 0.94 seconds
Started Apr 25 12:32:18 PM PDT 24
Finished Apr 25 12:32:20 PM PDT 24
Peak memory 195456 kb
Host smart-e64dc9b3-0657-4ea4-ac65-abe52fe2c5a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=650835593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.650835593
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.460572262
Short name T927
Test name
Test status
Simulation time 35137394 ps
CPU time 0.79 seconds
Started Apr 25 12:32:17 PM PDT 24
Finished Apr 25 12:32:19 PM PDT 24
Peak memory 196332 kb
Host smart-7777ad79-cb27-4efe-8d42-a28e6e0caf1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460572262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.460572262
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3415692696
Short name T864
Test name
Test status
Simulation time 212305885 ps
CPU time 0.98 seconds
Started Apr 25 12:32:26 PM PDT 24
Finished Apr 25 12:32:29 PM PDT 24
Peak memory 196584 kb
Host smart-7a32d5a9-92bf-413d-85a3-a9fca97ca978
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3415692696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3415692696
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3070967793
Short name T908
Test name
Test status
Simulation time 622454327 ps
CPU time 1.13 seconds
Started Apr 25 12:33:29 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 195084 kb
Host smart-5df8ad92-bcdf-4b10-9ef5-99d0356913e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070967793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3070967793
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2811431146
Short name T945
Test name
Test status
Simulation time 451385193 ps
CPU time 1.22 seconds
Started Apr 25 12:32:17 PM PDT 24
Finished Apr 25 12:32:19 PM PDT 24
Peak memory 196964 kb
Host smart-43bf850f-7530-4aaa-912c-a8fb579b698b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2811431146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2811431146
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.609721508
Short name T931
Test name
Test status
Simulation time 323934971 ps
CPU time 1.36 seconds
Started Apr 25 12:32:19 PM PDT 24
Finished Apr 25 12:32:21 PM PDT 24
Peak memory 196604 kb
Host smart-2d4336f3-0120-4345-bc07-b163fb2dddbb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609721508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.609721508
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1936741353
Short name T879
Test name
Test status
Simulation time 52282201 ps
CPU time 1.09 seconds
Started Apr 25 12:32:20 PM PDT 24
Finished Apr 25 12:32:22 PM PDT 24
Peak memory 195872 kb
Host smart-b584a92f-4b98-4b5b-9b94-5bb2f75b5065
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1936741353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1936741353
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1425474173
Short name T880
Test name
Test status
Simulation time 236432903 ps
CPU time 1.15 seconds
Started Apr 25 12:32:18 PM PDT 24
Finished Apr 25 12:32:21 PM PDT 24
Peak memory 195856 kb
Host smart-8b00a799-ed97-4c2d-85cb-1b76a527bfdf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425474173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1425474173
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2476323991
Short name T892
Test name
Test status
Simulation time 135450472 ps
CPU time 0.82 seconds
Started Apr 25 12:32:19 PM PDT 24
Finished Apr 25 12:32:21 PM PDT 24
Peak memory 195296 kb
Host smart-1908046a-50b1-4701-9180-cafd93f23792
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2476323991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2476323991
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.294389249
Short name T881
Test name
Test status
Simulation time 107449419 ps
CPU time 1.03 seconds
Started Apr 25 12:32:20 PM PDT 24
Finished Apr 25 12:32:22 PM PDT 24
Peak memory 196792 kb
Host smart-e12528a3-87a0-4e20-8ff3-bde143ed47fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294389249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.294389249
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4108171599
Short name T936
Test name
Test status
Simulation time 331298036 ps
CPU time 1.6 seconds
Started Apr 25 12:32:19 PM PDT 24
Finished Apr 25 12:32:22 PM PDT 24
Peak memory 196832 kb
Host smart-7d844eaa-c6c1-4028-9847-df897db2adf4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4108171599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4108171599
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3773266959
Short name T885
Test name
Test status
Simulation time 224845832 ps
CPU time 1.19 seconds
Started Apr 25 12:32:19 PM PDT 24
Finished Apr 25 12:32:21 PM PDT 24
Peak memory 195916 kb
Host smart-6d7b763a-16df-47fb-a301-9f0cd93e4299
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773266959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3773266959
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4169731792
Short name T929
Test name
Test status
Simulation time 38944881 ps
CPU time 0.85 seconds
Started Apr 25 12:32:19 PM PDT 24
Finished Apr 25 12:32:21 PM PDT 24
Peak memory 195492 kb
Host smart-2be5f9ab-30ff-4714-83e4-45498ae51240
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4169731792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4169731792
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1796257296
Short name T920
Test name
Test status
Simulation time 242021368 ps
CPU time 1.34 seconds
Started Apr 25 12:32:17 PM PDT 24
Finished Apr 25 12:32:19 PM PDT 24
Peak memory 196660 kb
Host smart-ebf9d51a-1556-40c9-bc4d-8a8b3cb2fce1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796257296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1796257296
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2341514070
Short name T870
Test name
Test status
Simulation time 188233056 ps
CPU time 0.92 seconds
Started Apr 25 12:32:07 PM PDT 24
Finished Apr 25 12:32:09 PM PDT 24
Peak memory 196624 kb
Host smart-0e5ff3ac-8989-4776-b16d-009dc641c017
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2341514070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2341514070
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.122993445
Short name T896
Test name
Test status
Simulation time 146517243 ps
CPU time 0.96 seconds
Started Apr 25 12:32:04 PM PDT 24
Finished Apr 25 12:32:06 PM PDT 24
Peak memory 196484 kb
Host smart-39ba9410-0885-4b6d-8c40-67bcbcc25aac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122993445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.122993445
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.694681697
Short name T857
Test name
Test status
Simulation time 1559084934 ps
CPU time 1.39 seconds
Started Apr 25 12:32:17 PM PDT 24
Finished Apr 25 12:32:19 PM PDT 24
Peak memory 196840 kb
Host smart-e452ee1a-1f03-416f-9fc6-eb5c72136a4a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=694681697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.694681697
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1375758145
Short name T856
Test name
Test status
Simulation time 320353601 ps
CPU time 1.58 seconds
Started Apr 25 12:32:19 PM PDT 24
Finished Apr 25 12:32:21 PM PDT 24
Peak memory 196772 kb
Host smart-b4275857-5d33-4777-9af7-ff579ddaba1b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375758145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1375758145
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.959440476
Short name T876
Test name
Test status
Simulation time 150106093 ps
CPU time 1.16 seconds
Started Apr 25 12:32:19 PM PDT 24
Finished Apr 25 12:32:21 PM PDT 24
Peak memory 195912 kb
Host smart-8d040527-0f88-4852-8eea-b9cd7ec7dd6d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=959440476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.959440476
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2724671688
Short name T871
Test name
Test status
Simulation time 202559538 ps
CPU time 1.43 seconds
Started Apr 25 12:32:18 PM PDT 24
Finished Apr 25 12:32:20 PM PDT 24
Peak memory 196712 kb
Host smart-430a63c6-2023-4488-b027-030d850dc891
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724671688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2724671688
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3724618321
Short name T941
Test name
Test status
Simulation time 34223749 ps
CPU time 0.83 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:28 PM PDT 24
Peak memory 195304 kb
Host smart-aaf2c035-04c2-4ddf-b48f-88ee7c48730c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3724618321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3724618321
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.476460447
Short name T893
Test name
Test status
Simulation time 125961756 ps
CPU time 0.96 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:27 PM PDT 24
Peak memory 196740 kb
Host smart-1b759e7a-088c-4db6-9b24-130f20fcd8a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476460447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.476460447
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3350788033
Short name T865
Test name
Test status
Simulation time 134776365 ps
CPU time 0.98 seconds
Started Apr 25 12:32:23 PM PDT 24
Finished Apr 25 12:32:24 PM PDT 24
Peak memory 196568 kb
Host smart-1df8f619-6b30-4c65-abc6-94b4b200f804
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3350788033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3350788033
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2933991726
Short name T849
Test name
Test status
Simulation time 82983453 ps
CPU time 1 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:28 PM PDT 24
Peak memory 196848 kb
Host smart-a8916ed1-326f-4da3-982e-0ab3fe07e5f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933991726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2933991726
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2722162072
Short name T854
Test name
Test status
Simulation time 241483410 ps
CPU time 1.06 seconds
Started Apr 25 12:33:41 PM PDT 24
Finished Apr 25 12:33:44 PM PDT 24
Peak memory 195836 kb
Host smart-a7d555fd-cb91-4926-8c0a-2cef94d63c26
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2722162072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2722162072
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1992594919
Short name T925
Test name
Test status
Simulation time 54698006 ps
CPU time 1.31 seconds
Started Apr 25 12:32:23 PM PDT 24
Finished Apr 25 12:32:25 PM PDT 24
Peak memory 196884 kb
Host smart-517c063a-16c4-427f-b1f1-97ecc81efc0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992594919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1992594919
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2149316041
Short name T858
Test name
Test status
Simulation time 63744282 ps
CPU time 0.94 seconds
Started Apr 25 12:32:26 PM PDT 24
Finished Apr 25 12:32:29 PM PDT 24
Peak memory 195924 kb
Host smart-c4fbc174-7cde-43a2-b609-d1b2e48dc9bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2149316041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2149316041
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4013458503
Short name T910
Test name
Test status
Simulation time 153499106 ps
CPU time 1.51 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:28 PM PDT 24
Peak memory 196548 kb
Host smart-1080c6df-c745-4ea4-8ca7-ca3c38b1c4f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013458503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4013458503
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3162220721
Short name T862
Test name
Test status
Simulation time 271055483 ps
CPU time 1.32 seconds
Started Apr 25 12:32:26 PM PDT 24
Finished Apr 25 12:32:29 PM PDT 24
Peak memory 196892 kb
Host smart-159a6bae-0e75-4c58-98fd-1bc5bab44291
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3162220721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3162220721
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3081092566
Short name T928
Test name
Test status
Simulation time 58006434 ps
CPU time 0.96 seconds
Started Apr 25 12:33:40 PM PDT 24
Finished Apr 25 12:33:44 PM PDT 24
Peak memory 196608 kb
Host smart-ad27a89b-b3d4-431c-89c7-760c409642ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081092566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3081092566
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1109311410
Short name T860
Test name
Test status
Simulation time 77265250 ps
CPU time 0.76 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:28 PM PDT 24
Peak memory 196236 kb
Host smart-1eb01ba9-3a87-4e5a-aead-2bec2bbce5e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1109311410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1109311410
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3549804836
Short name T939
Test name
Test status
Simulation time 128780141 ps
CPU time 0.88 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:28 PM PDT 24
Peak memory 196364 kb
Host smart-54157f8c-9bae-4c3d-b250-1428e4487e1b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549804836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3549804836
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2452635837
Short name T886
Test name
Test status
Simulation time 51617698 ps
CPU time 0.83 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:27 PM PDT 24
Peak memory 195380 kb
Host smart-1fa75d5b-3bf3-4e8f-9e03-65610efc7bcb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2452635837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2452635837
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1823199230
Short name T946
Test name
Test status
Simulation time 183028507 ps
CPU time 1.01 seconds
Started Apr 25 12:33:41 PM PDT 24
Finished Apr 25 12:33:44 PM PDT 24
Peak memory 196572 kb
Host smart-3be749f1-bbf9-4b29-9707-3a4166ea1d35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823199230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1823199230
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2452740878
Short name T867
Test name
Test status
Simulation time 596027911 ps
CPU time 1.01 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:28 PM PDT 24
Peak memory 196564 kb
Host smart-1520ccab-6a9b-4cd0-8702-91ce29472603
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2452740878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2452740878
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2124840333
Short name T898
Test name
Test status
Simulation time 250240165 ps
CPU time 1.17 seconds
Started Apr 25 12:32:24 PM PDT 24
Finished Apr 25 12:32:27 PM PDT 24
Peak memory 197996 kb
Host smart-90e22b1e-0b41-4a13-818f-08145fded35d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124840333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2124840333
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2393418502
Short name T868
Test name
Test status
Simulation time 523448713 ps
CPU time 1.01 seconds
Started Apr 25 12:32:09 PM PDT 24
Finished Apr 25 12:32:10 PM PDT 24
Peak memory 196616 kb
Host smart-10595bdc-e0ea-41e6-94ea-acc68ff3b814
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2393418502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2393418502
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1817380095
Short name T933
Test name
Test status
Simulation time 34925986 ps
CPU time 1 seconds
Started Apr 25 12:32:10 PM PDT 24
Finished Apr 25 12:32:13 PM PDT 24
Peak memory 195900 kb
Host smart-6a2cef4f-06ce-4dba-b662-ac436dc317d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817380095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1817380095
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3903566135
Short name T926
Test name
Test status
Simulation time 58611908 ps
CPU time 1.21 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:28 PM PDT 24
Peak memory 195800 kb
Host smart-b830d82e-1103-4b63-a9a8-540bd7733464
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3903566135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3903566135
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3199185751
Short name T919
Test name
Test status
Simulation time 157821003 ps
CPU time 1.13 seconds
Started Apr 25 12:32:25 PM PDT 24
Finished Apr 25 12:32:28 PM PDT 24
Peak memory 195944 kb
Host smart-8d1408f9-7877-48a1-a8ab-811eec0fd649
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199185751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3199185751
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1141826745
Short name T853
Test name
Test status
Simulation time 161679417 ps
CPU time 0.92 seconds
Started Apr 25 12:32:23 PM PDT 24
Finished Apr 25 12:32:24 PM PDT 24
Peak memory 197432 kb
Host smart-b4a60a38-1528-49b1-ba3c-b6cecbc8d2fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1141826745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1141826745
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3509390615
Short name T884
Test name
Test status
Simulation time 61069659 ps
CPU time 1.09 seconds
Started Apr 25 12:32:24 PM PDT 24
Finished Apr 25 12:32:26 PM PDT 24
Peak memory 198128 kb
Host smart-632c3579-46ea-4e2d-a5d9-745f1cc18bee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509390615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3509390615
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.135999559
Short name T861
Test name
Test status
Simulation time 223852400 ps
CPU time 0.98 seconds
Started Apr 25 12:32:26 PM PDT 24
Finished Apr 25 12:32:29 PM PDT 24
Peak memory 195604 kb
Host smart-2f68370a-a068-4da7-b822-507bd4c960af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=135999559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.135999559
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2538337881
Short name T913
Test name
Test status
Simulation time 274809382 ps
CPU time 1.14 seconds
Started Apr 25 12:33:41 PM PDT 24
Finished Apr 25 12:33:44 PM PDT 24
Peak memory 195820 kb
Host smart-ae3e6461-c3aa-4827-b5ae-5b317b5b039b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538337881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2538337881
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3903447400
Short name T915
Test name
Test status
Simulation time 69817995 ps
CPU time 1.11 seconds
Started Apr 25 12:33:41 PM PDT 24
Finished Apr 25 12:33:44 PM PDT 24
Peak memory 196776 kb
Host smart-d62ce4fd-05f5-46b4-9d8e-9c5cfc87bfef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3903447400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3903447400
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1082003488
Short name T855
Test name
Test status
Simulation time 346441482 ps
CPU time 0.93 seconds
Started Apr 25 12:32:27 PM PDT 24
Finished Apr 25 12:32:30 PM PDT 24
Peak memory 196620 kb
Host smart-ba6d9866-0457-47ce-83a0-191dc1f43392
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082003488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1082003488
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4058958880
Short name T891
Test name
Test status
Simulation time 661731457 ps
CPU time 1.13 seconds
Started Apr 25 12:32:32 PM PDT 24
Finished Apr 25 12:32:35 PM PDT 24
Peak memory 198032 kb
Host smart-1dcffdff-928f-4d97-8a2b-bdc745941d9b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4058958880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.4058958880
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1100523303
Short name T924
Test name
Test status
Simulation time 395310862 ps
CPU time 1.46 seconds
Started Apr 25 12:32:31 PM PDT 24
Finished Apr 25 12:32:33 PM PDT 24
Peak memory 196732 kb
Host smart-5b6cfa04-e17d-4865-8e8a-994403d1dd5e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100523303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1100523303
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4107060173
Short name T874
Test name
Test status
Simulation time 32882944 ps
CPU time 0.82 seconds
Started Apr 25 12:32:31 PM PDT 24
Finished Apr 25 12:32:32 PM PDT 24
Peak memory 196104 kb
Host smart-1637ff59-d065-4d65-aafc-eb76e865cb99
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4107060173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4107060173
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3653772933
Short name T899
Test name
Test status
Simulation time 100591129 ps
CPU time 0.77 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:35 PM PDT 24
Peak memory 195320 kb
Host smart-24b4d224-1010-47d9-ac0c-f8501f1e070d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653772933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3653772933
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1481507834
Short name T869
Test name
Test status
Simulation time 166376748 ps
CPU time 1.34 seconds
Started Apr 25 12:32:30 PM PDT 24
Finished Apr 25 12:32:32 PM PDT 24
Peak memory 197060 kb
Host smart-3efb40a1-002e-441f-b5de-744966808f5b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1481507834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1481507834
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2102136335
Short name T903
Test name
Test status
Simulation time 179121272 ps
CPU time 1.39 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:36 PM PDT 24
Peak memory 196956 kb
Host smart-5bab84b8-afa5-4820-8f8a-2355d3836515
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102136335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2102136335
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1259930404
Short name T894
Test name
Test status
Simulation time 185726724 ps
CPU time 1.55 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:37 PM PDT 24
Peak memory 196380 kb
Host smart-dd2b5cf5-506a-4b75-8300-06cab0c8cf70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1259930404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1259930404
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2422463181
Short name T863
Test name
Test status
Simulation time 86584287 ps
CPU time 1.28 seconds
Started Apr 25 12:32:32 PM PDT 24
Finished Apr 25 12:32:34 PM PDT 24
Peak memory 195772 kb
Host smart-949fc512-08d6-4453-a7f6-f3003656a043
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422463181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2422463181
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2803154481
Short name T850
Test name
Test status
Simulation time 186629611 ps
CPU time 1.34 seconds
Started Apr 25 12:32:33 PM PDT 24
Finished Apr 25 12:32:37 PM PDT 24
Peak memory 196904 kb
Host smart-857bcb9f-a794-450d-81b4-3d186f83f7bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2803154481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2803154481
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3148535780
Short name T917
Test name
Test status
Simulation time 173317470 ps
CPU time 1.18 seconds
Started Apr 25 12:32:31 PM PDT 24
Finished Apr 25 12:32:33 PM PDT 24
Peak memory 195908 kb
Host smart-b9d270ae-c443-4017-8cc7-eb76da1d9ee3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148535780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3148535780
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3366011123
Short name T911
Test name
Test status
Simulation time 92141500 ps
CPU time 0.89 seconds
Started Apr 25 12:32:30 PM PDT 24
Finished Apr 25 12:32:32 PM PDT 24
Peak memory 195860 kb
Host smart-3aaa3ef9-b623-472a-bc36-d570cd8bef45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3366011123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3366011123
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3465942203
Short name T904
Test name
Test status
Simulation time 111767535 ps
CPU time 0.84 seconds
Started Apr 25 12:32:32 PM PDT 24
Finished Apr 25 12:32:35 PM PDT 24
Peak memory 195464 kb
Host smart-3c57659c-bebd-4d71-a4d2-6f3eb5a268cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465942203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3465942203
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2188905544
Short name T866
Test name
Test status
Simulation time 263899775 ps
CPU time 1.16 seconds
Started Apr 25 12:32:05 PM PDT 24
Finished Apr 25 12:32:08 PM PDT 24
Peak memory 196652 kb
Host smart-724e461f-054d-4571-b429-c16567a6d64e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2188905544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2188905544
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.946050691
Short name T938
Test name
Test status
Simulation time 28528230 ps
CPU time 0.79 seconds
Started Apr 25 12:32:05 PM PDT 24
Finished Apr 25 12:32:07 PM PDT 24
Peak memory 195476 kb
Host smart-2f83e3dd-de43-4590-a1e1-e32304f53ab2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946050691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.946050691
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.387837331
Short name T943
Test name
Test status
Simulation time 161860171 ps
CPU time 0.87 seconds
Started Apr 25 12:32:06 PM PDT 24
Finished Apr 25 12:32:08 PM PDT 24
Peak memory 195588 kb
Host smart-ae660a7b-b54a-4cae-be51-db20a7282436
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=387837331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.387837331
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4137768417
Short name T940
Test name
Test status
Simulation time 107004134 ps
CPU time 0.71 seconds
Started Apr 25 12:32:07 PM PDT 24
Finished Apr 25 12:32:09 PM PDT 24
Peak memory 196280 kb
Host smart-c5185cbb-b255-4573-9361-0d5ae594fbbe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137768417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4137768417
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3685042543
Short name T890
Test name
Test status
Simulation time 56057337 ps
CPU time 1.43 seconds
Started Apr 25 12:32:13 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 196668 kb
Host smart-8f43b33a-deb5-42b4-8c9f-dd67922f4dd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3685042543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3685042543
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1327501841
Short name T877
Test name
Test status
Simulation time 285558471 ps
CPU time 1.27 seconds
Started Apr 25 12:32:10 PM PDT 24
Finished Apr 25 12:32:13 PM PDT 24
Peak memory 198032 kb
Host smart-a56d16f7-bbf8-42fb-a013-c3b3ee6ef84a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327501841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1327501841
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2973044025
Short name T887
Test name
Test status
Simulation time 174287878 ps
CPU time 1.44 seconds
Started Apr 25 12:32:14 PM PDT 24
Finished Apr 25 12:32:17 PM PDT 24
Peak memory 195696 kb
Host smart-14336bb9-3baa-4f99-ad50-5cdd2168b287
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2973044025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2973044025
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1161880459
Short name T873
Test name
Test status
Simulation time 142729284 ps
CPU time 0.96 seconds
Started Apr 25 12:32:12 PM PDT 24
Finished Apr 25 12:32:15 PM PDT 24
Peak memory 195152 kb
Host smart-dfacb6d5-1892-40a2-af2e-2b1515d8b7ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161880459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1161880459
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2093993432
Short name T902
Test name
Test status
Simulation time 174392616 ps
CPU time 1.24 seconds
Started Apr 25 12:32:11 PM PDT 24
Finished Apr 25 12:32:13 PM PDT 24
Peak memory 196808 kb
Host smart-0a8fb2e6-2051-459d-8bec-095367b27f7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2093993432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2093993432
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3181115910
Short name T895
Test name
Test status
Simulation time 187939208 ps
CPU time 1.27 seconds
Started Apr 25 12:32:12 PM PDT 24
Finished Apr 25 12:32:16 PM PDT 24
Peak memory 196596 kb
Host smart-5ff981e3-638d-4f7d-91b6-3b39e0bdc6cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181115910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3181115910
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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