Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4263404	1			T22	1		T23	1		T24	56
all_pins[1]	4263404	1			T22	1		T23	1		T24	56
all_pins[2]	4263404	1			T22	1		T23	1		T24	56
all_pins[3]	4263404	1			T22	1		T23	1		T24	56
all_pins[4]	4263404	1			T22	1		T23	1		T24	56
all_pins[5]	4263404	1			T22	1		T23	1		T24	56
all_pins[6]	4263404	1			T22	1		T23	1		T24	56
all_pins[7]	4263404	1			T22	1		T23	1		T24	56
all_pins[8]	4263404	1			T22	1		T23	1		T24	56
all_pins[9]	4263404	1			T22	1		T23	1		T24	56
all_pins[10]	4263404	1			T22	1		T23	1		T24	56
all_pins[11]	4263404	1			T22	1		T23	1		T24	56
all_pins[12]	4263404	1			T22	1		T23	1		T24	56
all_pins[13]	4263404	1			T22	1		T23	1		T24	56
all_pins[14]	4263404	1			T22	1		T23	1		T24	56
all_pins[15]	4263404	1			T22	1		T23	1		T24	56
all_pins[16]	4263404	1			T22	1		T23	1		T24	56
all_pins[17]	4263404	1			T22	1		T23	1		T24	56
all_pins[18]	4263404	1			T22	1		T23	1		T24	56
all_pins[19]	4263404	1			T22	1		T23	1		T24	56
all_pins[20]	4263404	1			T22	1		T23	1		T24	56
all_pins[21]	4263404	1			T22	1		T23	1		T24	56
all_pins[22]	4263404	1			T22	1		T23	1		T24	56
all_pins[23]	4263404	1			T22	1		T23	1		T24	56
all_pins[24]	4263404	1			T22	1		T23	1		T24	56
all_pins[25]	4263404	1			T22	1		T23	1		T24	56
all_pins[26]	4263404	1			T22	1		T23	1		T24	56
all_pins[27]	4263404	1			T22	1		T23	1		T24	56
all_pins[28]	4263404	1			T22	1		T23	1		T24	56
all_pins[29]	4263404	1			T22	1		T23	1		T24	56
all_pins[30]	4263404	1			T22	1		T23	1		T24	56
all_pins[31]	4263404	1			T22	1		T23	1		T24	56

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	84694266	1			T22	32		T23	32		T24	979
values[0x1]	51734662	1			T24	813		T27	626		T29	2780
transitions[0x0=>0x1]	30978714	1			T24	435		T27	324		T29	1703
transitions[0x1=>0x0]	30978556	1			T24	434		T27	323		T29	1703

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2651441	1			T22	1		T23	1		T24	35
all_pins[0]	values[0x1]	1611963	1			T24	21		T27	18		T29	85
all_pins[0]	transitions[0x0=>0x1]	996231	1			T24	10		T27	12		T29	40
all_pins[0]	transitions[0x1=>0x0]	1003451	1			T24	12		T27	14		T29	49
all_pins[1]	values[0x0]	2649486	1			T22	1		T23	1		T24	35
all_pins[1]	values[0x1]	1613918	1			T24	21		T27	16		T29	46
all_pins[1]	transitions[0x0=>0x1]	967265	1			T24	14		T27	10		T29	38
all_pins[1]	transitions[0x1=>0x0]	965310	1			T24	14		T27	12		T29	77
all_pins[2]	values[0x0]	2652704	1			T22	1		T23	1		T24	33
all_pins[2]	values[0x1]	1610700	1			T24	23		T27	24		T29	106
all_pins[2]	transitions[0x0=>0x1]	963737	1			T24	17		T27	13		T29	91
all_pins[2]	transitions[0x1=>0x0]	966955	1			T24	15		T27	5		T29	31
all_pins[3]	values[0x0]	2649874	1			T22	1		T23	1		T24	30
all_pins[3]	values[0x1]	1613530	1			T24	26		T27	22		T29	96
all_pins[3]	transitions[0x0=>0x1]	966915	1			T24	13		T27	8		T29	46
all_pins[3]	transitions[0x1=>0x0]	964085	1			T24	10		T27	10		T29	56
all_pins[4]	values[0x0]	2640494	1			T22	1		T23	1		T24	27
all_pins[4]	values[0x1]	1622910	1			T24	29		T27	19		T29	103
all_pins[4]	transitions[0x0=>0x1]	970344	1			T24	16		T27	10		T29	51
all_pins[4]	transitions[0x1=>0x0]	960964	1			T24	13		T27	13		T29	44
all_pins[5]	values[0x0]	2643644	1			T22	1		T23	1		T24	36
all_pins[5]	values[0x1]	1619760	1			T24	20		T27	18		T29	107
all_pins[5]	transitions[0x0=>0x1]	966728	1			T24	10		T27	9		T29	59
all_pins[5]	transitions[0x1=>0x0]	969878	1			T24	19		T27	10		T29	55
all_pins[6]	values[0x0]	2646992	1			T22	1		T23	1		T24	22
all_pins[6]	values[0x1]	1616412	1			T24	34		T27	18		T29	77
all_pins[6]	transitions[0x0=>0x1]	966536	1			T24	22		T27	11		T29	34
all_pins[6]	transitions[0x1=>0x0]	969884	1			T24	8		T27	11		T29	64
all_pins[7]	values[0x0]	2643924	1			T22	1		T23	1		T24	22
all_pins[7]	values[0x1]	1619480	1			T24	34		T27	21		T29	87
all_pins[7]	transitions[0x0=>0x1]	969431	1			T24	13		T27	14		T29	51
all_pins[7]	transitions[0x1=>0x0]	966363	1			T24	13		T27	11		T29	41
all_pins[8]	values[0x0]	2645208	1			T22	1		T23	1		T24	42
all_pins[8]	values[0x1]	1618196	1			T24	14		T27	18		T29	75
all_pins[8]	transitions[0x0=>0x1]	967134	1			T24	4		T27	9		T29	41
all_pins[8]	transitions[0x1=>0x0]	968418	1			T24	24		T27	12		T29	53
all_pins[9]	values[0x0]	2646299	1			T22	1		T23	1		T24	29
all_pins[9]	values[0x1]	1617105	1			T24	27		T27	13		T29	55
all_pins[9]	transitions[0x0=>0x1]	967166	1			T24	21		T27	7		T29	29
all_pins[9]	transitions[0x1=>0x0]	968257	1			T24	8		T27	12		T29	49
all_pins[10]	values[0x0]	2648974	1			T22	1		T23	1		T24	27
all_pins[10]	values[0x1]	1614430	1			T24	29		T27	19		T29	75
all_pins[10]	transitions[0x0=>0x1]	965816	1			T24	12		T27	13		T29	64
all_pins[10]	transitions[0x1=>0x0]	968491	1			T24	10		T27	7		T29	44
all_pins[11]	values[0x0]	2648584	1			T22	1		T23	1		T24	36
all_pins[11]	values[0x1]	1614820	1			T24	20		T27	28		T29	90
all_pins[11]	transitions[0x0=>0x1]	966817	1			T24	11		T27	15		T29	58
all_pins[11]	transitions[0x1=>0x0]	966427	1			T24	20		T27	6		T29	43
all_pins[12]	values[0x0]	2643431	1			T22	1		T23	1		T24	23
all_pins[12]	values[0x1]	1619973	1			T24	33		T27	20		T29	87
all_pins[12]	transitions[0x0=>0x1]	969780	1			T24	18		T27	6		T29	49
all_pins[12]	transitions[0x1=>0x0]	964627	1			T24	5		T27	14		T29	52
all_pins[13]	values[0x0]	2645350	1			T22	1		T23	1		T24	29
all_pins[13]	values[0x1]	1618054	1			T24	27		T27	25		T29	110
all_pins[13]	transitions[0x0=>0x1]	967484	1			T24	9		T27	12		T29	70
all_pins[13]	transitions[0x1=>0x0]	969403	1			T24	15		T27	7		T29	47
all_pins[14]	values[0x0]	2647502	1			T22	1		T23	1		T24	27
all_pins[14]	values[0x1]	1615902	1			T24	29		T27	19		T29	85
all_pins[14]	transitions[0x0=>0x1]	967325	1			T24	15		T27	5		T29	32
all_pins[14]	transitions[0x1=>0x0]	969477	1			T24	13		T27	11		T29	57
all_pins[15]	values[0x0]	2644473	1			T22	1		T23	1		T24	33
all_pins[15]	values[0x1]	1618931	1			T24	23		T27	19		T29	96
all_pins[15]	transitions[0x0=>0x1]	969658	1			T24	12		T27	8		T29	68
all_pins[15]	transitions[0x1=>0x0]	966629	1			T24	18		T27	8		T29	57
all_pins[16]	values[0x0]	2644953	1			T22	1		T23	1		T24	35
all_pins[16]	values[0x1]	1618451	1			T24	21		T27	23		T29	61
all_pins[16]	transitions[0x0=>0x1]	966092	1			T24	15		T27	15		T29	42
all_pins[16]	transitions[0x1=>0x0]	966572	1			T24	17		T27	11		T29	77
all_pins[17]	values[0x0]	2645615	1			T22	1		T23	1		T24	35
all_pins[17]	values[0x1]	1617789	1			T24	21		T27	21		T29	85
all_pins[17]	transitions[0x0=>0x1]	967131	1			T24	13		T27	10		T29	56
all_pins[17]	transitions[0x1=>0x0]	967793	1			T24	13		T27	12		T29	32
all_pins[18]	values[0x0]	2645881	1			T22	1		T23	1		T24	27
all_pins[18]	values[0x1]	1617523	1			T24	29		T27	18		T29	95
all_pins[18]	transitions[0x0=>0x1]	966263	1			T24	20		T27	11		T29	67
all_pins[18]	transitions[0x1=>0x0]	966529	1			T24	12		T27	14		T29	57
all_pins[19]	values[0x0]	2645616	1			T22	1		T23	1		T24	27
all_pins[19]	values[0x1]	1617788	1			T24	29		T27	20		T29	79
all_pins[19]	transitions[0x0=>0x1]	967406	1			T24	16		T27	10		T29	55
all_pins[19]	transitions[0x1=>0x0]	967141	1			T24	16		T27	8		T29	71
all_pins[20]	values[0x0]	2642341	1			T22	1		T23	1		T24	34
all_pins[20]	values[0x1]	1621063	1			T24	22		T27	18		T29	79
all_pins[20]	transitions[0x0=>0x1]	968702	1			T24	13		T27	8		T29	52
all_pins[20]	transitions[0x1=>0x0]	965427	1			T24	20		T27	10		T29	52
all_pins[21]	values[0x0]	2645531	1			T22	1		T23	1		T24	31
all_pins[21]	values[0x1]	1617873	1			T24	25		T27	17		T29	112
all_pins[21]	transitions[0x0=>0x1]	966475	1			T24	17		T27	7		T29	71
all_pins[21]	transitions[0x1=>0x0]	969665	1			T24	14		T27	8		T29	38
all_pins[22]	values[0x0]	2647510	1			T22	1		T23	1		T24	27
all_pins[22]	values[0x1]	1615894	1			T24	29		T27	14		T29	100
all_pins[22]	transitions[0x0=>0x1]	965723	1			T24	13		T27	7		T29	54
all_pins[22]	transitions[0x1=>0x0]	967702	1			T24	9		T27	10		T29	66
all_pins[23]	values[0x0]	2644454	1			T22	1		T23	1		T24	32
all_pins[23]	values[0x1]	1618950	1			T24	24		T27	25		T29	79
all_pins[23]	transitions[0x0=>0x1]	967266	1			T24	10		T27	14		T29	48
all_pins[23]	transitions[0x1=>0x0]	964210	1			T24	15		T27	3		T29	69
all_pins[24]	values[0x0]	2646122	1			T22	1		T23	1		T24	23
all_pins[24]	values[0x1]	1617282	1			T24	33		T27	22		T29	80
all_pins[24]	transitions[0x0=>0x1]	966102	1			T24	16		T27	10		T29	51
all_pins[24]	transitions[0x1=>0x0]	967770	1			T24	7		T27	13		T29	50
all_pins[25]	values[0x0]	2642327	1			T22	1		T23	1		T24	30
all_pins[25]	values[0x1]	1621077	1			T24	26		T27	21		T29	86
all_pins[25]	transitions[0x0=>0x1]	970361	1			T24	11		T27	9		T29	55
all_pins[25]	transitions[0x1=>0x0]	966566	1			T24	18		T27	10		T29	49
all_pins[26]	values[0x0]	2650369	1			T22	1		T23	1		T24	35
all_pins[26]	values[0x1]	1613035	1			T24	21		T27	22		T29	96
all_pins[26]	transitions[0x0=>0x1]	965578	1			T24	8		T27	13		T29	49
all_pins[26]	transitions[0x1=>0x0]	973620	1			T24	13		T27	12		T29	39
all_pins[27]	values[0x0]	2655098	1			T22	1		T23	1		T24	31
all_pins[27]	values[0x1]	1608306	1			T24	25		T27	24		T29	100
all_pins[27]	transitions[0x0=>0x1]	962531	1			T24	14		T27	12		T29	50
all_pins[27]	transitions[0x1=>0x0]	967260	1			T24	10		T27	10		T29	46
all_pins[28]	values[0x0]	2645412	1			T22	1		T23	1		T24	29
all_pins[28]	values[0x1]	1617992	1			T24	27		T27	17		T29	86
all_pins[28]	transitions[0x0=>0x1]	971241	1			T24	13		T27	5		T29	58
all_pins[28]	transitions[0x1=>0x0]	961555	1			T24	11		T27	12		T29	72
all_pins[29]	values[0x0]	2645709	1			T22	1		T23	1		T24	33
all_pins[29]	values[0x1]	1617695	1			T24	23		T27	13		T29	105
all_pins[29]	transitions[0x0=>0x1]	965194	1			T24	15		T27	6		T29	68
all_pins[29]	transitions[0x1=>0x0]	965491	1			T24	19		T27	10		T29	49
all_pins[30]	values[0x0]	2654885	1			T22	1		T23	1		T24	32
all_pins[30]	values[0x1]	1608519	1			T24	24		T27	13		T29	63
all_pins[30]	transitions[0x0=>0x1]	961044	1			T24	12		T27	10		T29	30
all_pins[30]	transitions[0x1=>0x0]	970220	1			T24	11		T27	10		T29	72
all_pins[31]	values[0x0]	2644063	1			T22	1		T23	1		T24	32
all_pins[31]	values[0x1]	1619341	1			T24	24		T27	21		T29	94
all_pins[31]	transitions[0x0=>0x1]	973238	1			T24	12		T27	15		T29	76
all_pins[31]	transitions[0x1=>0x0]	962416	1			T24	12		T27	7		T29	45