Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14195989	1			T22	424		T23	1		T24	882
all_values[1]	14195989	1			T22	424		T23	1		T24	882
all_values[2]	14195989	1			T22	424		T23	1		T24	882
all_values[3]	14195989	1			T22	424		T23	1		T24	882
all_values[4]	14195989	1			T22	424		T23	1		T24	882
all_values[5]	14195989	1			T22	424		T23	1		T24	882
all_values[6]	14195989	1			T22	424		T23	1		T24	882
all_values[7]	14195989	1			T22	424		T23	1		T24	882
all_values[8]	14195989	1			T22	424		T23	1		T24	882
all_values[9]	14195989	1			T22	424		T23	1		T24	882
all_values[10]	14195989	1			T22	424		T23	1		T24	882
all_values[11]	14195989	1			T22	424		T23	1		T24	882
all_values[12]	14195989	1			T22	424		T23	1		T24	882
all_values[13]	14195989	1			T22	424		T23	1		T24	882
all_values[14]	14195989	1			T22	424		T23	1		T24	882
all_values[15]	14195989	1			T22	424		T23	1		T24	882
all_values[16]	14195989	1			T22	424		T23	1		T24	882
all_values[17]	14195989	1			T22	424		T23	1		T24	882
all_values[18]	14195989	1			T22	424		T23	1		T24	882
all_values[19]	14195989	1			T22	424		T23	1		T24	882
all_values[20]	14195989	1			T22	424		T23	1		T24	882
all_values[21]	14195989	1			T22	424		T23	1		T24	882
all_values[22]	14195989	1			T22	424		T23	1		T24	882
all_values[23]	14195989	1			T22	424		T23	1		T24	882
all_values[24]	14195989	1			T22	424		T23	1		T24	882
all_values[25]	14195989	1			T22	424		T23	1		T24	882
all_values[26]	14195989	1			T22	424		T23	1		T24	882
all_values[27]	14195989	1			T22	424		T23	1		T24	882
all_values[28]	14195989	1			T22	424		T23	1		T24	882
all_values[29]	14195989	1			T22	424		T23	1		T24	882
all_values[30]	14195989	1			T22	424		T23	1		T24	882
all_values[31]	14195989	1			T22	424		T23	1		T24	882

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

260826748

1

T22

13568

T23

32

T24

28224

auto[1]

193444900

1

T29

6088

T41

2815

T42

15037

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104579998

1

T22

13568

T23

32

T24

28224

auto[1]

349691650

1

T29

10343

T41

4815

T42

26948

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

449203451

1

T22

13568

T23

32

T24

28224

auto[1]

5068197

1

T42

1074

T32

231

T43

2214

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2686634	1			T22	424		T23	1		T24	882
all_values[0]	auto[0]	auto[0]	auto[1]	5373689	1			T29	136		T41	66		T42	459
all_values[0]	auto[0]	auto[1]	auto[0]	581631	1			T29	18		T41	14		T42	25
all_values[0]	auto[0]	auto[1]	auto[1]	5395816	1			T29	181		T41	82		T42	357
all_values[0]	auto[1]	auto[0]	auto[1]	79752	1			T42	25		T32	5		T43	38
all_values[0]	auto[1]	auto[1]	auto[1]	78467	1			T42	16		T32	6		T43	36
all_values[1]	auto[0]	auto[0]	auto[0]	2678176	1			T22	424		T23	1		T24	882
all_values[1]	auto[0]	auto[0]	auto[1]	5390383	1			T29	213		T41	89		T42	400
all_values[1]	auto[0]	auto[1]	auto[0]	589800	1			T29	33		T41	15		T42	81
all_values[1]	auto[0]	auto[1]	auto[1]	5379588	1			T29	91		T41	64		T42	346
all_values[1]	auto[1]	auto[0]	auto[1]	79754	1			T42	16		T32	2		T43	36
all_values[1]	auto[1]	auto[1]	auto[1]	78288	1			T42	17		T32	5		T43	35
all_values[2]	auto[0]	auto[0]	auto[0]	2696016	1			T22	424		T23	1		T24	882
all_values[2]	auto[0]	auto[0]	auto[1]	5414304	1			T29	131		T41	92		T42	413
all_values[2]	auto[0]	auto[1]	auto[0]	583389	1			T29	28		T41	16		T42	59
all_values[2]	auto[0]	auto[1]	auto[1]	5343657	1			T29	198		T41	33		T42	412
all_values[2]	auto[1]	auto[0]	auto[1]	79368	1			T42	18		T32	4		T43	35
all_values[2]	auto[1]	auto[1]	auto[1]	79255	1			T42	13		T32	3		T43	33
all_values[3]	auto[0]	auto[0]	auto[0]	2687968	1			T22	424		T23	1		T24	882
all_values[3]	auto[0]	auto[0]	auto[1]	5366789	1			T29	128		T41	96		T42	354
all_values[3]	auto[0]	auto[1]	auto[0]	591843	1			T29	35		T41	9		T42	53
all_values[3]	auto[0]	auto[1]	auto[1]	5390965	1			T29	194		T41	66		T42	451
all_values[3]	auto[1]	auto[0]	auto[1]	79467	1			T42	11		T32	7		T43	31
all_values[3]	auto[1]	auto[1]	auto[1]	78957	1			T42	21		T32	2		T43	36
all_values[4]	auto[0]	auto[0]	auto[0]	2678399	1			T22	424		T23	1		T24	882
all_values[4]	auto[0]	auto[0]	auto[1]	5365541	1			T29	167		T41	67		T42	355
all_values[4]	auto[0]	auto[1]	auto[0]	580886	1			T29	14		T41	10		T42	53
all_values[4]	auto[0]	auto[1]	auto[1]	5412137	1			T29	194		T41	106		T42	449
all_values[4]	auto[1]	auto[0]	auto[1]	78993	1			T42	13		T32	2		T43	37
all_values[4]	auto[1]	auto[1]	auto[1]	80033	1			T42	22		T32	6		T43	31
all_values[5]	auto[0]	auto[0]	auto[0]	2670940	1			T22	424		T23	1		T24	882
all_values[5]	auto[0]	auto[0]	auto[1]	5365855	1			T29	92		T41	78		T42	418
all_values[5]	auto[0]	auto[1]	auto[0]	587820	1			T29	30		T41	18		T42	39
all_values[5]	auto[0]	auto[1]	auto[1]	5413311	1			T29	212		T41	50		T42	404
all_values[5]	auto[1]	auto[0]	auto[1]	78999	1			T42	20		T32	5		T43	36
all_values[5]	auto[1]	auto[1]	auto[1]	79064	1			T42	25		T32	3		T43	34
all_values[6]	auto[0]	auto[0]	auto[0]	2681266	1			T22	424		T23	1		T24	882
all_values[6]	auto[0]	auto[0]	auto[1]	5392934	1			T29	180		T41	102		T42	416
all_values[6]	auto[0]	auto[1]	auto[0]	590182	1			T29	33		T41	17		T42	16
all_values[6]	auto[0]	auto[1]	auto[1]	5373070	1			T29	137		T41	53		T42	475
all_values[6]	auto[1]	auto[0]	auto[1]	79457	1			T42	13		T32	5		T43	40
all_values[6]	auto[1]	auto[1]	auto[1]	79080	1			T42	17		T43	34		T1	33
all_values[7]	auto[0]	auto[0]	auto[0]	2676948	1			T22	424		T23	1		T24	882
all_values[7]	auto[0]	auto[0]	auto[1]	5404648	1			T29	189		T41	72		T42	392
all_values[7]	auto[0]	auto[1]	auto[0]	585634	1			T29	42		T41	6		T42	71
all_values[7]	auto[0]	auto[1]	auto[1]	5370727	1			T29	144		T41	95		T42	434
all_values[7]	auto[1]	auto[0]	auto[1]	78869	1			T42	20		T32	3		T43	41
all_values[7]	auto[1]	auto[1]	auto[1]	79163	1			T42	18		T32	6		T43	37
all_values[8]	auto[0]	auto[0]	auto[0]	2685482	1			T22	424		T23	1		T24	882
all_values[8]	auto[0]	auto[0]	auto[1]	5374931	1			T29	169		T41	58		T42	470
all_values[8]	auto[0]	auto[1]	auto[0]	582314	1			T29	49		T41	9		T42	33
all_values[8]	auto[0]	auto[1]	auto[1]	5394883	1			T29	130		T41	95		T42	361
all_values[8]	auto[1]	auto[0]	auto[1]	79398	1			T42	21		T32	5		T43	29
all_values[8]	auto[1]	auto[1]	auto[1]	78981	1			T42	12		T32	1		T43	36
all_values[9]	auto[0]	auto[0]	auto[0]	2679905	1			T22	424		T23	1		T24	882
all_values[9]	auto[0]	auto[0]	auto[1]	5366791	1			T29	178		T41	78		T42	423
all_values[9]	auto[0]	auto[1]	auto[0]	586031	1			T29	40		T41	9		T42	59
all_values[9]	auto[0]	auto[1]	auto[1]	5404675	1			T29	114		T41	87		T42	370
all_values[9]	auto[1]	auto[0]	auto[1]	79084	1			T42	20		T32	5		T43	38
all_values[9]	auto[1]	auto[1]	auto[1]	79503	1			T42	12		T32	3		T43	35
all_values[10]	auto[0]	auto[0]	auto[0]	2675167	1			T22	424		T23	1		T24	882
all_values[10]	auto[0]	auto[0]	auto[1]	5427748	1			T29	204		T41	59		T42	312
all_values[10]	auto[0]	auto[1]	auto[0]	579450	1			T29	34		T41	17		T42	114
all_values[10]	auto[0]	auto[1]	auto[1]	5355397	1			T29	142		T41	85		T42	480
all_values[10]	auto[1]	auto[0]	auto[1]	78820	1			T42	10		T32	4		T43	28
all_values[10]	auto[1]	auto[1]	auto[1]	79407	1			T42	22		T32	3		T43	43
all_values[11]	auto[0]	auto[0]	auto[0]	2685273	1			T22	424		T23	1		T24	882
all_values[11]	auto[0]	auto[0]	auto[1]	5373173	1			T29	172		T41	91		T42	385
all_values[11]	auto[0]	auto[1]	auto[0]	587058	1			T29	17		T41	11		T42	48
all_values[11]	auto[0]	auto[1]	auto[1]	5392097	1			T29	150		T41	62		T42	467
all_values[11]	auto[1]	auto[0]	auto[1]	79129	1			T42	14		T32	3		T43	43
all_values[11]	auto[1]	auto[1]	auto[1]	79259	1			T42	20		T32	3		T43	29
all_values[12]	auto[0]	auto[0]	auto[0]	2684885	1			T22	424		T23	1		T24	882
all_values[12]	auto[0]	auto[0]	auto[1]	5386005	1			T29	143		T41	54		T42	373
all_values[12]	auto[0]	auto[1]	auto[0]	587017	1			T29	30		T41	17		T42	130
all_values[12]	auto[0]	auto[1]	auto[1]	5379851	1			T29	178		T41	99		T42	378
all_values[12]	auto[1]	auto[0]	auto[1]	79195	1			T42	15		T32	3		T43	27
all_values[12]	auto[1]	auto[1]	auto[1]	79036	1			T42	17		T32	5		T43	39
all_values[13]	auto[0]	auto[0]	auto[0]	2680532	1			T22	424		T23	1		T24	882
all_values[13]	auto[0]	auto[0]	auto[1]	5387886	1			T29	166		T41	70		T42	349
all_values[13]	auto[0]	auto[1]	auto[0]	589094	1			T29	25		T41	8		T42	72
all_values[13]	auto[0]	auto[1]	auto[1]	5380120	1			T29	182		T41	91		T42	424
all_values[13]	auto[1]	auto[0]	auto[1]	79622	1			T42	15		T32	3		T43	38
all_values[13]	auto[1]	auto[1]	auto[1]	78735	1			T42	20		T32	3		T43	34
all_values[14]	auto[0]	auto[0]	auto[0]	2682762	1			T22	424		T23	1		T24	882
all_values[14]	auto[0]	auto[0]	auto[1]	5397042	1			T29	173		T41	129		T42	454
all_values[14]	auto[0]	auto[1]	auto[0]	589405	1			T29	31		T41	8		T42	90
all_values[14]	auto[0]	auto[1]	auto[1]	5368682	1			T29	148		T41	45		T42	364
all_values[14]	auto[1]	auto[0]	auto[1]	78876	1			T42	26		T32	6		T43	24
all_values[14]	auto[1]	auto[1]	auto[1]	79222	1			T42	13		T32	2		T43	45
all_values[15]	auto[0]	auto[0]	auto[0]	2690002	1			T22	424		T23	1		T24	882
all_values[15]	auto[0]	auto[0]	auto[1]	5352683	1			T29	139		T41	107		T42	470
all_values[15]	auto[0]	auto[1]	auto[0]	590634	1			T29	35		T42	90		T32	22
all_values[15]	auto[0]	auto[1]	auto[1]	5404119	1			T29	188		T41	28		T42	293
all_values[15]	auto[1]	auto[0]	auto[1]	79302	1			T42	17		T43	24		T1	45
all_values[15]	auto[1]	auto[1]	auto[1]	79249	1			T42	15		T32	5		T43	41
all_values[16]	auto[0]	auto[0]	auto[0]	2678328	1			T22	424		T23	1		T24	882
all_values[16]	auto[0]	auto[0]	auto[1]	5419508	1			T29	227		T41	74		T42	434
all_values[16]	auto[0]	auto[1]	auto[0]	576151	1			T29	22		T41	22		T42	71
all_values[16]	auto[0]	auto[1]	auto[1]	5363489	1			T29	106		T41	66		T42	353
all_values[16]	auto[1]	auto[0]	auto[1]	79739	1			T42	16		T32	6		T43	35
all_values[16]	auto[1]	auto[1]	auto[1]	78774	1			T42	17		T32	1		T43	24
all_values[17]	auto[0]	auto[0]	auto[0]	2680476	1			T22	424		T23	1		T24	882
all_values[17]	auto[0]	auto[0]	auto[1]	5423562	1			T29	198		T41	95		T42	470
all_values[17]	auto[0]	auto[1]	auto[0]	580701	1			T29	17		T41	8		T42	29
all_values[17]	auto[0]	auto[1]	auto[1]	5353304	1			T29	167		T41	71		T42	342
all_values[17]	auto[1]	auto[0]	auto[1]	79138	1			T42	22		T32	2		T43	38
all_values[17]	auto[1]	auto[1]	auto[1]	78808	1			T42	14		T32	5		T43	37
all_values[18]	auto[0]	auto[0]	auto[0]	2687562	1			T22	424		T23	1		T24	882
all_values[18]	auto[0]	auto[0]	auto[1]	5370840	1			T29	175		T41	93		T42	527
all_values[18]	auto[0]	auto[1]	auto[0]	581898	1			T29	19		T41	3		T42	45
all_values[18]	auto[0]	auto[1]	auto[1]	5397476	1			T29	165		T41	84		T42	297
all_values[18]	auto[1]	auto[0]	auto[1]	79438	1			T42	22		T32	6		T43	33
all_values[18]	auto[1]	auto[1]	auto[1]	78775	1			T42	15		T32	3		T43	40
all_values[19]	auto[0]	auto[0]	auto[0]	2683305	1			T22	424		T23	1		T24	882
all_values[19]	auto[0]	auto[0]	auto[1]	5422976	1			T29	147		T41	53		T42	402
all_values[19]	auto[0]	auto[1]	auto[0]	588697	1			T29	25		T41	9		T42	78
all_values[19]	auto[0]	auto[1]	auto[1]	5342269	1			T29	147		T41	118		T42	403
all_values[19]	auto[1]	auto[0]	auto[1]	79705	1			T42	15		T32	3		T43	20
all_values[19]	auto[1]	auto[1]	auto[1]	79037	1			T42	21		T32	3		T43	47
all_values[20]	auto[0]	auto[0]	auto[0]	2687921	1			T22	424		T23	1		T24	882
all_values[20]	auto[0]	auto[0]	auto[1]	5356826	1			T29	167		T41	64		T42	435
all_values[20]	auto[0]	auto[1]	auto[0]	585200	1			T29	42		T41	23		T42	57
all_values[20]	auto[0]	auto[1]	auto[1]	5407651	1			T29	132		T41	66		T42	422
all_values[20]	auto[1]	auto[0]	auto[1]	79096	1			T42	14		T32	6		T43	34
all_values[20]	auto[1]	auto[1]	auto[1]	79295	1			T42	12		T32	1		T43	30
all_values[21]	auto[0]	auto[0]	auto[0]	2674664	1			T22	424		T23	1		T24	882
all_values[21]	auto[0]	auto[0]	auto[1]	5384085	1			T29	136		T41	82		T42	353
all_values[21]	auto[0]	auto[1]	auto[0]	581044	1			T29	29		T41	18		T42	54
all_values[21]	auto[0]	auto[1]	auto[1]	5397757	1			T29	214		T41	49		T42	446
all_values[21]	auto[1]	auto[0]	auto[1]	79437	1			T42	14		T32	5		T43	43
all_values[21]	auto[1]	auto[1]	auto[1]	79002	1			T42	16		T32	2		T43	38
all_values[22]	auto[0]	auto[0]	auto[0]	2685810	1			T22	424		T23	1		T24	882
all_values[22]	auto[0]	auto[0]	auto[1]	5388273	1			T29	150		T41	67		T42	514
all_values[22]	auto[0]	auto[1]	auto[0]	589120	1			T29	13		T41	25		T42	41
all_values[22]	auto[0]	auto[1]	auto[1]	5374881	1			T29	168		T41	70		T42	331
all_values[22]	auto[1]	auto[0]	auto[1]	79453	1			T42	19		T32	2		T43	36
all_values[22]	auto[1]	auto[1]	auto[1]	78452	1			T42	13		T32	5		T43	27
all_values[23]	auto[0]	auto[0]	auto[0]	2683713	1			T22	424		T23	1		T24	882
all_values[23]	auto[0]	auto[0]	auto[1]	5398472	1			T29	175		T41	84		T42	507
all_values[23]	auto[0]	auto[1]	auto[0]	596601	1			T29	54		T41	13		T42	88
all_values[23]	auto[0]	auto[1]	auto[1]	5358910	1			T29	139		T41	82		T42	277
all_values[23]	auto[1]	auto[0]	auto[1]	79588	1			T42	25		T32	2		T43	30
all_values[23]	auto[1]	auto[1]	auto[1]	78705	1			T42	12		T32	3		T43	36
all_values[24]	auto[0]	auto[0]	auto[0]	2686551	1			T22	424		T23	1		T24	882
all_values[24]	auto[0]	auto[0]	auto[1]	5400551	1			T29	162		T41	59		T42	393
all_values[24]	auto[0]	auto[1]	auto[0]	583788	1			T29	57		T41	17		T42	112
all_values[24]	auto[0]	auto[1]	auto[1]	5366551	1			T29	136		T41	79		T42	329
all_values[24]	auto[1]	auto[0]	auto[1]	79223	1			T42	19		T32	4		T43	32
all_values[24]	auto[1]	auto[1]	auto[1]	79325	1			T42	15		T32	3		T43	32
all_values[25]	auto[0]	auto[0]	auto[0]	2685852	1			T22	424		T23	1		T24	882
all_values[25]	auto[0]	auto[0]	auto[1]	5379734	1			T29	129		T41	68		T42	451
all_values[25]	auto[0]	auto[1]	auto[0]	594196	1			T29	63		T41	11		T42	61
all_values[25]	auto[0]	auto[1]	auto[1]	5377773	1			T29	169		T41	91		T42	320
all_values[25]	auto[1]	auto[0]	auto[1]	79382	1			T42	12		T32	1		T43	38
all_values[25]	auto[1]	auto[1]	auto[1]	79052	1			T42	12		T32	2		T43	36
all_values[26]	auto[0]	auto[0]	auto[0]	2678821	1			T22	424		T23	1		T24	882
all_values[26]	auto[0]	auto[0]	auto[1]	5383313	1			T29	149		T41	71		T42	328
all_values[26]	auto[0]	auto[1]	auto[0]	587355	1			T29	27		T41	16		T42	58
all_values[26]	auto[0]	auto[1]	auto[1]	5388011	1			T29	177		T41	80		T42	429
all_values[26]	auto[1]	auto[0]	auto[1]	79711	1			T42	13		T32	2		T43	40
all_values[26]	auto[1]	auto[1]	auto[1]	78778	1			T42	21		T32	6		T43	28
all_values[27]	auto[0]	auto[0]	auto[0]	2678846	1			T22	424		T23	1		T24	882
all_values[27]	auto[0]	auto[0]	auto[1]	5429357	1			T29	206		T41	50		T42	350
all_values[27]	auto[0]	auto[1]	auto[0]	581934	1			T29	13		T41	22		T42	27
all_values[27]	auto[0]	auto[1]	auto[1]	5347477	1			T29	153		T41	74		T42	547
all_values[27]	auto[1]	auto[0]	auto[1]	79556	1			T42	13		T32	6		T43	36
all_values[27]	auto[1]	auto[1]	auto[1]	78819	1			T42	13		T32	1		T43	34
all_values[28]	auto[0]	auto[0]	auto[0]	2674556	1			T22	424		T23	1		T24	882
all_values[28]	auto[0]	auto[0]	auto[1]	5375722	1			T29	119		T41	87		T42	433
all_values[28]	auto[0]	auto[1]	auto[0]	583895	1			T29	57		T41	20		T42	50
all_values[28]	auto[0]	auto[1]	auto[1]	5403007	1			T29	162		T41	59		T42	362
all_values[28]	auto[1]	auto[0]	auto[1]	79358	1			T42	18		T32	2		T43	31
all_values[28]	auto[1]	auto[1]	auto[1]	79451	1			T42	15		T32	4		T43	38
all_values[29]	auto[0]	auto[0]	auto[0]	2685429	1			T22	424		T23	1		T24	882
all_values[29]	auto[0]	auto[0]	auto[1]	5376732	1			T29	129		T41	58		T42	370
all_values[29]	auto[0]	auto[1]	auto[0]	579053	1			T29	37		T41	54		T42	59
all_values[29]	auto[0]	auto[1]	auto[1]	5396472	1			T29	199		T41	61		T42	452
all_values[29]	auto[1]	auto[0]	auto[1]	79133	1			T42	19		T32	5		T43	39
all_values[29]	auto[1]	auto[1]	auto[1]	79170	1			T42	17		T32	5		T43	33
all_values[30]	auto[0]	auto[0]	auto[0]	2684382	1			T22	424		T23	1		T24	882
all_values[30]	auto[0]	auto[0]	auto[1]	5419875	1			T29	244		T41	70		T42	464
all_values[30]	auto[0]	auto[1]	auto[0]	584297	1			T29	7		T41	17		T42	43
all_values[30]	auto[0]	auto[1]	auto[1]	5348725	1			T29	111		T41	83		T42	375
all_values[30]	auto[1]	auto[0]	auto[1]	79849	1			T42	20		T32	6		T43	23
all_values[30]	auto[1]	auto[1]	auto[1]	78861	1			T42	15		T32	4		T43	35
all_values[31]	auto[0]	auto[0]	auto[0]	2682661	1			T22	424		T23	1		T24	882
all_values[31]	auto[0]	auto[0]	auto[1]	5378000	1			T29	158		T41	85		T42	433
all_values[31]	auto[0]	auto[1]	auto[0]	584648	1			T29	20		T41	6		T42	38
all_values[31]	auto[0]	auto[1]	auto[1]	5392377	1			T29	164		T41	73		T42	417
all_values[31]	auto[1]	auto[0]	auto[1]	79397	1			T42	13		T32	3		T43	37
all_values[31]	auto[1]	auto[1]	auto[1]	78906	1			T42	18		T32	4		T43	31

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal