Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[1]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[2]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[3]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[4]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[5]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[6]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[7]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[8]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[9]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[10]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[11]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[12]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[13]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[14]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[15]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[16]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[17]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[18]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[19]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[20]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[21]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[22]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[23]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[24]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[25]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[26]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[27]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[28]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[29]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[30]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[31]	13939232	1			T22	692		T23	1		T24	882

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

269038154

1

T22

6603

T23

32

T24

13932

auto[1]

177017270

1

T22

15541

T24

14292

T25

17895

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

357267065

1

T22

13783

T23

32

T24

28224

auto[1]

88788359

1

T22

8361

T25

5116

T26

4119

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

331580610

1

T22

13531

T23

32

T24

28224

auto[1]

114474814

1

T22

8613

T25

10813

T26

8098

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5204021	1			T22	85		T23	1		T24	435
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3761027	1			T22	226		T24	447		T25	280
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1396945	1			T22	134		T25	47		T26	63
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1801703	1			T25	30		T26	18		T30	78
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	393036	1			T22	140		T25	252		T26	149
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1382500	1			T22	107		T25	73		T26	50
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5216386	1			T22	80		T23	1		T24	414
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3755225	1			T22	189		T24	468		T25	225
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1391803	1			T22	124		T25	88		T26	97
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1800443	1			T25	41		T26	16		T30	118
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	394365	1			T22	142		T25	257		T26	128
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1381010	1			T22	157		T25	75		T26	52
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5205540	1			T22	83		T23	1		T24	404
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3755621	1			T22	228		T24	478		T25	209
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1397620	1			T22	94		T25	109		T26	50
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1799671	1			T25	40		T26	26		T30	142
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	394452	1			T22	164		T25	267		T26	187
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1386328	1			T22	123		T25	65		T26	81
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5220804	1			T22	78		T23	1		T24	422
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3746320	1			T22	209		T24	460		T25	267
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1395111	1			T22	157		T25	70		T26	68
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1801307	1			T25	37		T26	10		T30	206
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	393852	1			T22	116		T25	221		T26	139
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1381838	1			T22	132		T25	96		T26	68
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5208542	1			T22	82		T23	1		T24	410
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3753988	1			T22	234		T24	472		T25	244
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1396414	1			T22	116		T25	102		T26	89
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1799635	1			T25	41		T26	21		T30	126
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	395101	1			T22	140		T25	229		T26	120
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1385552	1			T22	120		T25	63		T26	69
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5209937	1			T22	77		T23	1		T24	454
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3752313	1			T22	221		T24	428		T25	275
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1398642	1			T22	146		T25	79		T26	63
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1800076	1			T25	36		T26	18		T30	104
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	392531	1			T22	126		T25	198		T26	190
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1385733	1			T22	122		T25	79		T26	46
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5220522	1			T22	75		T23	1		T24	425
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3754000	1			T22	258		T24	457		T25	210
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1399449	1			T22	104		T25	83		T26	55
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1793985	1			T25	37		T26	18		T30	143
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	390642	1			T22	127		T25	274		T26	184
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1380634	1			T22	128		T25	78		T26	62
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5215455	1			T22	82		T23	1		T24	478
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3751278	1			T22	184		T24	404		T25	228
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1393966	1			T22	130		T25	89		T26	64
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1803602	1			T25	52		T26	19		T30	103
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	394978	1			T22	166		T25	230		T26	148
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1379953	1			T22	130		T25	88		T26	53
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5213596	1			T22	71		T23	1		T24	474
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3752214	1			T22	220		T24	408		T25	325
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1398042	1			T22	118		T25	74		T26	79
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1801097	1			T25	45		T26	16		T30	92
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	393589	1			T22	133		T25	192		T26	153
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1380694	1			T22	150		T25	45		T26	45
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5220474	1			T22	74		T23	1		T24	460
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3746304	1			T22	205		T24	422		T25	245
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1394813	1			T22	146		T25	87		T26	76
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1798452	1			T25	38		T26	20		T30	143
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	395828	1			T22	132		T25	246		T26	152
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1383361	1			T22	135		T25	74		T26	59
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5210213	1			T22	83		T23	1		T24	392
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3764324	1			T22	218		T24	490		T25	279
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1393750	1			T22	132		T25	71		T26	57
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1797234	1			T25	38		T26	17		T30	149
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	394238	1			T22	138		T25	206		T26	207
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1379473	1			T22	121		T25	98		T26	76
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5210704	1			T22	79		T23	1		T24	406
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3751129	1			T22	200		T24	476		T25	215
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1395027	1			T22	130		T25	75		T26	84
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1801594	1			T25	44		T26	27		T30	139
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	393195	1			T22	165		T25	269		T26	211
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1387583	1			T22	118		T25	95		T26	55
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5201596	1			T22	80		T23	1		T24	371
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3755080	1			T22	253		T24	511		T25	297
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1399534	1			T22	123		T25	83		T26	57
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1802565	1			T25	31		T26	11		T30	152
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	395194	1			T22	130		T25	170		T26	175
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1385263	1			T22	106		T25	84		T26	78
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5194802	1			T22	72		T23	1		T24	396
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3768655	1			T22	232		T24	486		T25	269
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1395093	1			T22	132		T25	86		T26	46
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1799217	1			T25	27		T26	22		T30	139
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	396800	1			T22	140		T25	185		T26	176
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1384665	1			T22	116		T25	100		T26	77
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5200056	1			T22	83		T23	1		T24	480
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3758137	1			T22	172		T24	402		T25	273
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1398513	1			T22	138		T25	94		T26	50
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1801811	1			T25	35		T26	22		T30	102
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	394470	1			T22	125		T25	209		T26	213
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1386245	1			T22	174		T25	66		T26	47
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5208577	1			T22	72		T23	1		T24	432
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3750840	1			T22	223		T24	450		T25	232
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1396058	1			T22	125		T25	77		T26	103
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1805202	1			T25	34		T26	21		T30	124
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	395148	1			T22	152		T25	247		T26	155
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1383407	1			T22	120		T25	98		T26	48
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5206406	1			T22	79		T23	1		T24	452
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3764042	1			T22	196		T24	430		T25	214
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1394588	1			T22	138		T25	75		T26	43
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1797727	1			T25	46		T26	22		T30	108
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	392737	1			T22	149		T25	277		T26	216
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1383732	1			T22	130		T25	76		T26	72
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5210950	1			T22	68		T23	1		T24	492
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3757673	1			T22	237		T24	390		T25	240
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1391293	1			T22	143		T25	103		T26	59
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1801861	1			T25	33		T26	14		T30	143
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	394183	1			T22	134		T25	244		T26	174
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1383272	1			T22	110		T25	63		T26	63
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5221713	1			T22	79		T23	1		T24	443
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3752404	1			T22	196		T24	439		T25	215
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1392618	1			T22	130		T25	79		T26	70
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1803651	1			T25	39		T26	26		T30	98
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	394163	1			T22	128		T25	260		T26	193
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1374683	1			T22	159		T25	90		T26	69
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5212668	1			T22	71		T23	1		T24	444
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3761793	1			T22	240		T24	438		T25	335
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1386772	1			T22	134		T25	113		T26	50
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1805559	1			T25	25		T26	16		T30	143
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	393904	1			T22	117		T25	131		T26	160
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1378536	1			T22	130		T25	61		T26	87
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5213224	1			T22	67		T23	1		T24	513
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3760235	1			T22	226		T24	369		T25	209
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1390640	1			T22	144		T25	100		T26	54
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1804093	1			T25	38		T26	23		T30	131
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	394989	1			T22	143		T25	239		T26	182
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1376051	1			T22	112		T25	91		T26	46
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5202724	1			T22	65		T23	1		T24	443
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3768579	1			T22	216		T24	439		T25	281
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1389984	1			T22	127		T25	91		T26	58
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1809021	1			T25	25		T26	20		T30	126
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	393283	1			T22	146		T25	234		T26	154
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1375641	1			T22	138		T25	55		T26	64
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5211541	1			T22	74		T23	1		T24	396
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3761481	1			T22	213		T24	486		T25	276
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1391684	1			T22	150		T25	68		T26	47
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1804846	1			T25	35		T26	22		T30	91
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	391511	1			T22	145		T25	235		T26	201
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1378169	1			T22	110		T25	74		T26	80
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5222480	1			T22	83		T23	1		T24	406
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3755936	1			T22	183		T24	476		T25	283
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1395014	1			T22	90		T25	113		T26	68
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1798136	1			T25	28		T26	15		T30	127
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	391904	1			T22	138		T25	194		T26	145
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1375762	1			T22	198		T25	60		T26	79
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5220832	1			T22	72		T23	1		T24	461
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3751984	1			T22	246		T24	421		T25	228
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1391804	1			T22	102		T25	66		T26	53
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1803654	1			T25	33		T26	27		T30	177
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	395744	1			T22	166		T25	262		T26	215
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1375214	1			T22	106		T25	88		T26	45
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5210094	1			T22	87		T23	1		T24	433
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3762828	1			T22	224		T24	449		T25	287
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1391609	1			T22	137		T25	115		T26	31
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1802706	1			T25	23		T26	20		T30	150
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	396153	1			T22	132		T25	190		T26	172
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1375842	1			T22	112		T25	34		T26	93
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5219365	1			T22	72		T23	1		T24	343
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3757797	1			T22	209		T24	539		T25	248
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1387023	1			T22	131		T25	108		T26	50
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1807732	1			T25	38		T26	17		T30	102
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	392246	1			T22	142		T25	204		T26	128
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1375069	1			T22	138		T25	72		T26	104
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5203744	1			T22	81		T23	1		T24	432
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3761302	1			T22	208		T24	450		T25	302
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1388559	1			T22	112		T25	92		T26	91
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1807579	1			T25	23		T26	7		T30	74
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	395138	1			T22	123		T25	190		T26	101
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1382910	1			T22	168		T25	59		T26	60
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5221500	1			T22	76		T23	1		T24	454
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3750527	1			T22	219		T24	428		T25	277
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1388961	1			T22	125		T25	81		T26	80
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1804841	1			T25	46		T26	20		T30	201
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	391537	1			T22	144		T25	215		T26	136
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1381866	1			T22	128		T25	66		T26	38
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5208155	1			T22	79		T23	1		T24	494
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3758900	1			T22	228		T24	388		T25	255
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1392632	1			T22	141		T25	51		T26	52
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1802854	1			T25	34		T26	21		T30	154
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	393657	1			T22	124		T25	262		T26	173
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1383034	1			T22	120		T25	84		T26	63
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5214679	1			T22	62		T23	1		T24	441
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3752089	1			T22	219		T24	441		T25	219
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1392217	1			T22	147		T25	53		T26	64
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1804104	1			T25	38		T26	10		T30	148
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	396259	1			T22	122		T25	265		T26	140
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1379884	1			T22	142		T25	91		T26	92
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5210954	1			T22	79		T23	1		T24	432
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3759338	1			T22	196		T24	450		T25	282
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1388815	1			T22	153		T25	95		T26	42
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1804949	1			T25	32		T26	19		T30	163
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	395714	1			T22	116		T25	218		T26	214
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1379462	1			T22	148		T25	58		T26	85

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal