Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[1]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[2]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[3]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[4]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[5]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[6]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[7]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[8]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[9]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[10]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[11]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[12]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[13]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[14]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[15]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[16]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[17]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[18]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[19]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[20]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[21]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[22]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[23]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[24]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[25]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[26]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[27]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[28]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[29]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[30]	13939232	1			T22	692		T23	1		T24	882
bins_for_gpio_bits[31]	13939232	1			T22	692		T23	1		T24	882

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

269038154

1

T22

6603

T23

32

T24

13932

auto[1]

177017270

1

T22

15541

T24

14292

T25

17895

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

269029770

1

T22

6614

T23

32

T24

13932

auto[1]

177025654

1

T22

15530

T24

14292

T25

17888

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8155325	1			T22	187		T23	1		T24	435
bins_for_gpio_bits[0]	auto[0]	auto[1]	247054	1			T22	32		T25	12		T26	13
bins_for_gpio_bits[0]	auto[1]	auto[0]	247344	1			T22	32		T25	12		T26	13
bins_for_gpio_bits[0]	auto[1]	auto[1]	5289509	1			T22	441		T24	447		T25	593
bins_for_gpio_bits[1]	auto[0]	auto[0]	8161239	1			T22	175		T23	1		T24	414
bins_for_gpio_bits[1]	auto[0]	auto[1]	247111	1			T22	29		T25	15		T26	14
bins_for_gpio_bits[1]	auto[1]	auto[0]	247393	1			T22	29		T25	15		T26	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	5283489	1			T22	459		T24	468		T25	542
bins_for_gpio_bits[2]	auto[0]	auto[0]	8154760	1			T22	146		T23	1		T24	404
bins_for_gpio_bits[2]	auto[0]	auto[1]	247823	1			T22	31		T25	14		T26	7
bins_for_gpio_bits[2]	auto[1]	auto[0]	248071	1			T22	31		T25	14		T26	7
bins_for_gpio_bits[2]	auto[1]	auto[1]	5288578	1			T22	484		T24	478		T25	527
bins_for_gpio_bits[3]	auto[0]	auto[0]	8170309	1			T22	197		T23	1		T24	422
bins_for_gpio_bits[3]	auto[0]	auto[1]	246669	1			T22	39		T25	15		T26	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	246913	1			T22	38		T25	15		T26	15
bins_for_gpio_bits[3]	auto[1]	auto[1]	5275341	1			T22	418		T24	460		T25	569
bins_for_gpio_bits[4]	auto[0]	auto[0]	8156846	1			T22	166		T23	1		T24	410
bins_for_gpio_bits[4]	auto[0]	auto[1]	247485	1			T22	32		T25	17		T26	17
bins_for_gpio_bits[4]	auto[1]	auto[0]	247745	1			T22	32		T25	16		T26	17
bins_for_gpio_bits[4]	auto[1]	auto[1]	5287156	1			T22	462		T24	472		T25	519
bins_for_gpio_bits[5]	auto[0]	auto[0]	8161058	1			T22	186		T23	1		T24	454
bins_for_gpio_bits[5]	auto[0]	auto[1]	247373	1			T22	37		T25	13		T26	12
bins_for_gpio_bits[5]	auto[1]	auto[0]	247597	1			T22	37		T25	13		T26	12
bins_for_gpio_bits[5]	auto[1]	auto[1]	5283204	1			T22	432		T24	428		T25	539
bins_for_gpio_bits[6]	auto[0]	auto[0]	8166961	1			T22	148		T23	1		T24	425
bins_for_gpio_bits[6]	auto[0]	auto[1]	246763	1			T22	31		T25	15		T26	11
bins_for_gpio_bits[6]	auto[1]	auto[0]	246995	1			T22	31		T25	15		T26	11
bins_for_gpio_bits[6]	auto[1]	auto[1]	5278513	1			T22	482		T24	457		T25	547
bins_for_gpio_bits[7]	auto[0]	auto[0]	8165430	1			T22	179		T23	1		T24	478
bins_for_gpio_bits[7]	auto[0]	auto[1]	247302	1			T22	33		T25	13		T26	11
bins_for_gpio_bits[7]	auto[1]	auto[0]	247593	1			T22	33		T25	13		T26	11
bins_for_gpio_bits[7]	auto[1]	auto[1]	5278907	1			T22	447		T24	404		T25	533
bins_for_gpio_bits[8]	auto[0]	auto[0]	8165617	1			T22	160		T23	1		T24	474
bins_for_gpio_bits[8]	auto[0]	auto[1]	246865	1			T22	29		T25	14		T26	12
bins_for_gpio_bits[8]	auto[1]	auto[0]	247118	1			T22	29		T25	14		T26	12
bins_for_gpio_bits[8]	auto[1]	auto[1]	5279632	1			T22	474		T24	408		T25	548
bins_for_gpio_bits[9]	auto[0]	auto[0]	8166082	1			T22	183		T23	1		T24	460
bins_for_gpio_bits[9]	auto[0]	auto[1]	247387	1			T22	37		T25	15		T26	15
bins_for_gpio_bits[9]	auto[1]	auto[0]	247657	1			T22	37		T25	15		T26	15
bins_for_gpio_bits[9]	auto[1]	auto[1]	5278106	1			T22	435		T24	422		T25	550
bins_for_gpio_bits[10]	auto[0]	auto[0]	8153870	1			T22	179		T23	1		T24	392
bins_for_gpio_bits[10]	auto[0]	auto[1]	247071	1			T22	36		T25	16		T26	11
bins_for_gpio_bits[10]	auto[1]	auto[0]	247327	1			T22	36		T25	16		T26	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	5290964	1			T22	441		T24	490		T25	567
bins_for_gpio_bits[11]	auto[0]	auto[0]	8159409	1			T22	178		T23	1		T24	406
bins_for_gpio_bits[11]	auto[0]	auto[1]	247634	1			T22	31		T25	18		T26	11
bins_for_gpio_bits[11]	auto[1]	auto[0]	247916	1			T22	31		T25	18		T26	11
bins_for_gpio_bits[11]	auto[1]	auto[1]	5284273	1			T22	452		T24	476		T25	561
bins_for_gpio_bits[12]	auto[0]	auto[0]	8155767	1			T22	171		T23	1		T24	371
bins_for_gpio_bits[12]	auto[0]	auto[1]	247666	1			T22	33		T25	19		T26	9
bins_for_gpio_bits[12]	auto[1]	auto[0]	247928	1			T22	32		T25	19		T26	9
bins_for_gpio_bits[12]	auto[1]	auto[1]	5287871	1			T22	456		T24	511		T25	532
bins_for_gpio_bits[13]	auto[0]	auto[0]	8141938	1			T22	174		T23	1		T24	396
bins_for_gpio_bits[13]	auto[0]	auto[1]	246926	1			T22	30		T25	19		T26	9
bins_for_gpio_bits[13]	auto[1]	auto[0]	247174	1			T22	30		T25	19		T26	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	5303194	1			T22	458		T24	486		T25	535
bins_for_gpio_bits[14]	auto[0]	auto[0]	8152532	1			T22	192		T23	1		T24	480
bins_for_gpio_bits[14]	auto[0]	auto[1]	247574	1			T22	29		T25	15		T26	9
bins_for_gpio_bits[14]	auto[1]	auto[0]	247848	1			T22	29		T25	15		T26	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	5291278	1			T22	442		T24	402		T25	533
bins_for_gpio_bits[15]	auto[0]	auto[0]	8162204	1			T22	167		T23	1		T24	432
bins_for_gpio_bits[15]	auto[0]	auto[1]	247408	1			T22	31		T25	12		T26	15
bins_for_gpio_bits[15]	auto[1]	auto[0]	247633	1			T22	30		T25	12		T26	15
bins_for_gpio_bits[15]	auto[1]	auto[1]	5281987	1			T22	464		T24	450		T25	565
bins_for_gpio_bits[16]	auto[0]	auto[0]	8151535	1			T22	186		T23	1		T24	452
bins_for_gpio_bits[16]	auto[0]	auto[1]	246889	1			T22	31		T25	15		T26	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	247186	1			T22	31		T25	15		T26	8
bins_for_gpio_bits[16]	auto[1]	auto[1]	5293622	1			T22	444		T24	430		T25	552
bins_for_gpio_bits[17]	auto[0]	auto[0]	8155797	1			T22	172		T23	1		T24	492
bins_for_gpio_bits[17]	auto[0]	auto[1]	248062	1			T22	40		T25	20		T26	12
bins_for_gpio_bits[17]	auto[1]	auto[0]	248307	1			T22	39		T25	19		T26	12
bins_for_gpio_bits[17]	auto[1]	auto[1]	5287066	1			T22	441		T24	390		T25	527
bins_for_gpio_bits[18]	auto[0]	auto[0]	8171139	1			T22	177		T23	1		T24	443
bins_for_gpio_bits[18]	auto[0]	auto[1]	246534	1			T22	32		T25	11		T26	12
bins_for_gpio_bits[18]	auto[1]	auto[0]	246843	1			T22	32		T25	11		T26	12
bins_for_gpio_bits[18]	auto[1]	auto[1]	5274716	1			T22	451		T24	439		T25	554
bins_for_gpio_bits[19]	auto[0]	auto[0]	8157408	1			T22	168		T23	1		T24	444
bins_for_gpio_bits[19]	auto[0]	auto[1]	247348	1			T22	37		T25	22		T26	10
bins_for_gpio_bits[19]	auto[1]	auto[0]	247591	1			T22	37		T25	22		T26	10
bins_for_gpio_bits[19]	auto[1]	auto[1]	5286885	1			T22	450		T24	438		T25	505
bins_for_gpio_bits[20]	auto[0]	auto[0]	8161109	1			T22	176		T23	1		T24	513
bins_for_gpio_bits[20]	auto[0]	auto[1]	246615	1			T22	35		T25	19		T26	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	246848	1			T22	35		T25	19		T26	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	5284660	1			T22	446		T24	369		T25	520
bins_for_gpio_bits[21]	auto[0]	auto[0]	8153874	1			T22	161		T23	1		T24	443
bins_for_gpio_bits[21]	auto[0]	auto[1]	247583	1			T22	32		T25	16		T26	14
bins_for_gpio_bits[21]	auto[1]	auto[0]	247855	1			T22	31		T25	16		T26	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	5289920	1			T22	468		T24	439		T25	554
bins_for_gpio_bits[22]	auto[0]	auto[0]	8160727	1			T22	193		T23	1		T24	396
bins_for_gpio_bits[22]	auto[0]	auto[1]	247080	1			T22	31		T25	16		T26	11
bins_for_gpio_bits[22]	auto[1]	auto[0]	247344	1			T22	31		T25	16		T26	11
bins_for_gpio_bits[22]	auto[1]	auto[1]	5284081	1			T22	437		T24	486		T25	569
bins_for_gpio_bits[23]	auto[0]	auto[0]	8168596	1			T22	148		T23	1		T24	406
bins_for_gpio_bits[23]	auto[0]	auto[1]	246757	1			T22	25		T25	18		T26	11
bins_for_gpio_bits[23]	auto[1]	auto[0]	247034	1			T22	25		T25	17		T26	11
bins_for_gpio_bits[23]	auto[1]	auto[1]	5276845	1			T22	494		T24	476		T25	519
bins_for_gpio_bits[24]	auto[0]	auto[0]	8168955	1			T22	140		T23	1		T24	461
bins_for_gpio_bits[24]	auto[0]	auto[1]	247038	1			T22	34		T25	16		T26	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	247335	1			T22	34		T25	16		T26	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	5275904	1			T22	484		T24	421		T25	562
bins_for_gpio_bits[25]	auto[0]	auto[0]	8157059	1			T22	186		T23	1		T24	433
bins_for_gpio_bits[25]	auto[0]	auto[1]	247111	1			T22	39		T25	18		T26	7
bins_for_gpio_bits[25]	auto[1]	auto[0]	247350	1			T22	38		T25	17		T26	7
bins_for_gpio_bits[25]	auto[1]	auto[1]	5287712	1			T22	429		T24	449		T25	493
bins_for_gpio_bits[26]	auto[0]	auto[0]	8166916	1			T22	170		T23	1		T24	343
bins_for_gpio_bits[26]	auto[0]	auto[1]	246945	1			T22	34		T25	21		T26	13
bins_for_gpio_bits[26]	auto[1]	auto[0]	247204	1			T22	33		T25	20		T26	13
bins_for_gpio_bits[26]	auto[1]	auto[1]	5278167	1			T22	455		T24	539		T25	503
bins_for_gpio_bits[27]	auto[0]	auto[0]	8152173	1			T22	161		T23	1		T24	432
bins_for_gpio_bits[27]	auto[0]	auto[1]	247442	1			T22	32		T25	20		T26	21
bins_for_gpio_bits[27]	auto[1]	auto[0]	247709	1			T22	32		T25	20		T26	21
bins_for_gpio_bits[27]	auto[1]	auto[1]	5291908	1			T22	467		T24	450		T25	531
bins_for_gpio_bits[28]	auto[0]	auto[0]	8167074	1			T22	169		T23	1		T24	454
bins_for_gpio_bits[28]	auto[0]	auto[1]	247934	1			T22	33		T25	17		T26	19
bins_for_gpio_bits[28]	auto[1]	auto[0]	248228	1			T22	32		T25	16		T26	19
bins_for_gpio_bits[28]	auto[1]	auto[1]	5275996	1			T22	458		T24	428		T25	541
bins_for_gpio_bits[29]	auto[0]	auto[0]	8155534	1			T22	189		T23	1		T24	494
bins_for_gpio_bits[29]	auto[0]	auto[1]	247868	1			T22	32		T25	13		T26	12
bins_for_gpio_bits[29]	auto[1]	auto[0]	248107	1			T22	31		T25	13		T26	12
bins_for_gpio_bits[29]	auto[1]	auto[1]	5287723	1			T22	440		T24	388		T25	588
bins_for_gpio_bits[30]	auto[0]	auto[0]	8163436	1			T22	175		T23	1		T24	441
bins_for_gpio_bits[30]	auto[0]	auto[1]	247273	1			T22	35		T25	13		T26	13
bins_for_gpio_bits[30]	auto[1]	auto[0]	247564	1			T22	34		T25	13		T26	13
bins_for_gpio_bits[30]	auto[1]	auto[1]	5280959	1			T22	448		T24	441		T25	562
bins_for_gpio_bits[31]	auto[0]	auto[0]	8157575	1			T22	198		T23	1		T24	432
bins_for_gpio_bits[31]	auto[0]	auto[1]	246926	1			T22	35		T25	20		T26	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	247143	1			T22	34		T25	19		T26	9
bins_for_gpio_bits[31]	auto[1]	auto[1]	5287588	1			T22	425		T24	450		T25	538