Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8139811 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6056178 |
1 |
|
|
T29 |
179 |
|
T41 |
104 |
|
T42 |
406 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13425615 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
770374 |
1 |
|
|
T29 |
12 |
|
T41 |
3 |
|
T42 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8147852 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6048137 |
1 |
|
|
T29 |
205 |
|
T41 |
40 |
|
T42 |
552 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2633704 |
1 |
|
|
T29 |
92 |
|
T41 |
20 |
|
T42 |
285 |
| auto[1] |
auto[0] |
auto[1] |
383932 |
1 |
|
|
T29 |
8 |
|
T41 |
1 |
|
T42 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2644059 |
1 |
|
|
T29 |
101 |
|
T41 |
17 |
|
T42 |
244 |
| auto[1] |
auto[1] |
auto[1] |
386442 |
1 |
|
|
T29 |
4 |
|
T41 |
2 |
|
T42 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |