Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8148873 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6047116 |
1 |
|
|
T29 |
203 |
|
T41 |
113 |
|
T42 |
579 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2634638 |
1 |
|
|
T29 |
99 |
|
T41 |
43 |
|
T42 |
253 |
| auto[1] |
auto[0] |
auto[1] |
383920 |
1 |
|
|
T29 |
5 |
|
T41 |
2 |
|
T42 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2642572 |
1 |
|
|
T29 |
91 |
|
T41 |
64 |
|
T42 |
308 |
| auto[1] |
auto[1] |
auto[1] |
385986 |
1 |
|
|
T29 |
8 |
|
T41 |
4 |
|
T42 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |