Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8185986 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6010003 |
1 |
|
|
T29 |
172 |
|
T41 |
127 |
|
T42 |
502 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11739406 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
2456583 |
1 |
|
|
T29 |
50 |
|
T41 |
61 |
|
T42 |
121 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8170898 |
1 |
|
|
T22 |
424 |
|
T23 |
1 |
|
T24 |
882 |
| auto[1] |
6025091 |
1 |
|
|
T29 |
138 |
|
T41 |
122 |
|
T42 |
486 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1790943 |
1 |
|
|
T29 |
46 |
|
T41 |
16 |
|
T42 |
158 |
| auto[1] |
auto[0] |
auto[1] |
1233791 |
1 |
|
|
T29 |
32 |
|
T41 |
16 |
|
T42 |
81 |
| auto[1] |
auto[1] |
auto[0] |
1777565 |
1 |
|
|
T29 |
42 |
|
T41 |
45 |
|
T42 |
207 |
| auto[1] |
auto[1] |
auto[1] |
1222792 |
1 |
|
|
T29 |
18 |
|
T41 |
45 |
|
T42 |
40 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |